COVER
DATA SHEET
2G bits DDR3 SDRAM
EDJ2108DEBG (256M words
×
8 bits)
EDJ2116DEBG (128M words
×
16 bits)
Specifications
• Density: 2G bits
• Organization
— 32M words
×
8 bits
×
8 banks (EDJ2108DEBG)
— 16M words
×
16 bits
×
8 banks (EDJ2116DEBG)
• Package
— 78-ball FBGA (EDJ2108DEBG)
— 96-ball FBGA (EDJ2116DEBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.5V
±
0.075V
• Data rate
— 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max)
• 1KB page size (EDJ2108DEBG)
— Row address: A0 to A14
— Column address: A0 to A9
• 2KB page size (EDJ2116DEBG)
— Row address: A0 to A13
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_15
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14
• /CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C
≤
TC
≤
+85°C
3.9µs at +85°C < TC
≤
+95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
• Seamless BL4 access with bank-grouping
— Applied only for DDR3-1333 and 1600
Document. No. E1712E50 (Ver. 5.0)
Date Published July 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©
Elpida Memory, Inc. 2010-2012
EDJ2108DEBG, EDJ2116DEBG
Ordering Information
Part number
EDJ2108DEBG-MU-F
EDJ2108DEBG-JS-F
EDJ2108DEBG-GN-F
EDJ2108DEBG-DJ-F
EDJ2116DEBG-MU-F
EDJ2116DEBG-JS-F
EDJ2116DEBG-GN-F
EDJ2116DEBG-DJ-F
Die
revision
Organization
(words
×
bits)
256M
×
8
Internal
banks
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-2133 (14-14-14)
DDR3-1866 (13-13-13)
DDR3-1600 (11-11-11)
DDR3-1333 (9-9-9)
DDR3-2133 (14-14-14)
DDR3-1866 (13-13-13)
DDR3-1600 (11-11-11)
DDR3-1333 (9-9-9)
Package
78-ball FBGA
E
8
96-ball FBGA
128M
×
16
Part Number
E D J 21 08 D E BG - MU - F
Elpida Memory
Type
D: Packaged Device
Product Family
J: DDR3
Density / Bank
21: 2Gb / 8-bank
Organization
08: x8
16: x16
Power Supply, Interface
D: 1.5V, SSTL_15
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Speed
MU: DDR3-2133 (14-14-14)
JS: DDR3-1866 (13-13-13)
GN: DDR3-1600 (11-11-11)
DJ: DDR3-1333 (9-9-9)
Package
BG: FBGA
Die Rev.
Operating Frequency
Frequency (Mbps)
Speed
Grade
-MU
-JS
-GN
-DJ
667
667
667
CL5
CL6
800
800
800
800
CL7
1066
1066
1066
1066
CL8
1066
1066
1066
1066
CL9
1333
1333
1333
1333
CL10
1333
1333
1333
1333
CL11
1600
1600
1600
CL13
1866
1866
CL14
2133
speed bin
(CL-tRCD-tRP)
DDR3-2133
(14-14-14)
DDR3-1866
(13-13-13)
DDR3-1600
(11-11-11)
DDR3-1333
(9-9-9)
Detailed Information
For detailed electrical specification and further information, please refer to the DDR3 SDRAM General Functionality
and Electrical Condition data sheet (E1926E) and Addendum data sheet (E1928E).
Data Sheet E1712E50 (Ver. 5.0)
2
EDJ2108DEBG, EDJ2116DEBG
Pin Configurations
Pin Configurations (× 8 configuration)
/xxx indicates active low signal.
78-ball FBGA
1
A
VSS
B
VSS VSSQ
C
VDDQ
D
VSSQ
E
VREFDQ VDDQ
F
NC
G
ODT
H
NC
J
VSS
K
VDD
L
VSS
M
N
VSS /RESET A13
(Top view)
A14
A8
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
A3
A0
A12(/BC) BA1
VDD
BA0
BA2
NC
VREFCA VSS
/CS
/WE
A10(AP)
ZQ
NC
VDD
/CAS
/CK
VDD
CKE
VSS
/RAS
CK
VSS
NC
DQ6
/DQS
DQ4
VDD
DQ7
VSS
DQ5
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
DQ0
DM/TDQS
VSSQ VDDQ
2
VDD
3
NC
7
8
9
VDD
NU/(/TDQS)
VSS
Pin name
A0 to A14*
3
Function
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
Bank select
Data input/output
Differential data strobe
Termination data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
ODT control
Pin name
/RESET*
3
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
1
Function
Active low asynchronous reset
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage for CA
Reference pin for ZQ calibration
No connection
Not usable
BA0 to BA2*
3
DQ0 to DQ7
DQS, /DQS
TDQS, /TDQS
/CS*
3
/RAS, /CAS, /WE*
3
CKE*
3
CK, /CK
DM
ODT*
3
Notes: 1.
2.
3.
NU*
2
Not internally connected with die.
Don't connect. Internally connected.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1712E50 (Ver. 5.0)
3
EDJ2108DEBG, EDJ2116DEBG
Pin Configurations (× 16 configuration)
/xxx indicates active low signal.
96-ball FBGA
1
A
VDDQ DQU5 DQU7
B
VSSQ
C
VDDQ DQU3 DQU1
D
E
VSS
F
VDDQ DQL2 DQSL
G
VSSQ DQL6 /DQSL
H
VREFDQ VDDQ DQL4
J
NC
K
ODT
L
NC
M
VSS
N
VDD
P
VSS
R
VDD
T
VSS /RESET A13
NC
A8
VSS
A7
A9
A11
A6
VDD
A5
A2
A1
A4
VSS
A3
A0
A12(/BC) BA1
VDD
BA0
BA2
NC
VREFCA VSS
/CS
/WE
A10(AP)
ZQ
NC
VDD
/CAS
/CK
VDD
CKE
VSS
/RAS
CK
VSS
NC
DQL7 DQL5 VDDQ
VDD
VSS
VSSQ
DQL1 DQL3 VSSQ
VSSQ DQL0
DML
VSSQ VDDQ
VSSQ VDDQ DMU
DQSU DQU2 VDDQ
DQU0 VSSQ
VDD
VDD
VSS
/DQSU DQU6 VSSQ
DQU4 VDDQ
VSS
2
3
7
8
9
(Top view)
Pin name
A0 to A13*
2
Function
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
Bank select
Data input/output
Differential data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
ODT control
Pin name
/RESET*
2
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
1
Function
Active low asynchronous reset
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage for CA
Reference pin for ZQ calibration
No connection
BA0 to BA2*
2
DQU0 to DQU7
DQL0 to DQL7
DQSU, /DQSU
DQSL, /DQSL
/CS*
2
/RAS, /CAS, /WE*
2
CKE*
2
CK, /CK
DMU, DML
ODT*
2
Notes: 1.
2.
Not internally connected with die.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1712E50 (Ver. 5.0)
4
EDJ2108DEBG, EDJ2116DEBG
CONTENTS
Specifications ........................................................................................................................................ 1
Features ................................................................................................................................................ 1
Ordering Information ............................................................................................................................. 2
Part Number .......................................................................................................................................... 2
Operating Frequency ............................................................................................................................ 2
Detailed Information .............................................................................................................................. 2
Pin Configurations ................................................................................................................................. 3
1. Electrical Conditions ...................................................................................................................... 6
1.1
1.2
1.3
1.4
Absolute Maximum Ratings ..............................................................................................................6
Operating Temperature Condition ....................................................................................................6
Recommended DC Operating Conditions ........................................................................................7
IDD and IDDQ Measurement Conditions ..........................................................................................8
DC Characteristics .......................................................................................................................... 19
Pin Capacitance .............................................................................................................................. 21
Standard Speed Bins ...................................................................................................................... 23
78-ball FBGA .................................................................................................................................. 29
96-ball FBGA .................................................................................................................................. 30
2.
Electrical Specifications ............................................................................................................... 19
2.1
2.2
2.3
3.
Package Drawing ......................................................................................................................... 29
3.1
3.2
4.
Recommended Soldering Conditions .......................................................................................... 31
Data Sheet E1712E50 (Ver. 5.0)
5
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