PRELIMINARY
‡
512MB, 1GB, 2GB (x64, DR)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM UDIMM
DDR2 SDRAM
UNBUFFERED DIMM
Features
• 240-pin, dual in-line memory module (DIMM)
• Fast data transfer rates: PC2-3200 or PC2-4300
• Utilizes 400 MT/s and 533 MT/s DDR2 SDRAM
components
• 512MB (64 Meg x 64), 1GB (128 Meg x 64)
2GB (256 Meg x 64)
• V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• Commands entered on each rising CK edge
• DQS edge-aligned with data for READs
• DQS center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four or eight internal device banks for concurrent
operation
• Data mask (DM) for masking write data
• Programmable CAS# latency (CL): 3 and 4
• Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• READ burst interrupt supported by another READ
• WRITE burst interrupt supported by another WRITE
• Adjustable data-output drive strength
• Concurrent auto precharge option is supported
• Auto Refresh (CBR) and Self Refresh Mode
• 7.8125µs maximum average periodic refresh
interval
• 64ms, 8,192-cycle refresh
For the latest data sheet, please refer to the Micron
â
Web
site:
www.micron.com/moduleds
MT16HTF6464A – 512MB
MT16HTF12864A – 1GB (ADVANCE
‡
)
MT16HTF25664A – 2GB (ADVANCE
‡
)
Figure 1: 240-Pin DIMM (MO-237 R/C “B”)
•
•
•
•
Off-chip driver (OCD) impedance calibration
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
OPTIONS
MARKING
• Package
240-pin DIMM (standard)
240-pin DIMM (lead-free)
1
• Frequency/CAS Latency
2
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
NOTE:
G
Y
-53E
-40E
1. Consult factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) Latency.
Table 1:
Address Table
512MB
1GB
8K
16K (A0–A13)
4 (BA0, BA1)
512Mb (64 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1Gb (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
09005aef80f09068
HTF16C64_128_256x64AG_A.fm - Rev. A 11/03 EN
1
©2003 Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
512MB, 1GB, 2GB (x64, DR)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM UDIMM
Table 1: Key Timing Parameters
DATA RATE (MHz)
SPEED GRADE
-40E
-53E
CL = 3
400
400
CL = 4
400
533
t
RCD
(ns)
15
15
RP
(ns)
15
15
t
RC
(ns)
60
60
t
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
CONFIGURATION
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
MODULE
BANDWIDTH
3.2 GB/s
3.2 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
4.3 GB/s
4.3 GB/s
3.2 GB/s
3.2 GB/s
4.3 GB/s
4.3 GB/s
MEMORY CLOCK/
DATA RATE
5.0ns/400 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5.0ns/400 MT/s
3.75ns/533 MT/s
3.75ns/533 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
3-3-3
3-3-3
4-4-4
4-4-4
3-3-3
3-3-3
4-4-4
4-4-4
3-3-3
3-3-3
4-4-4
4-4-4
PART NUMBER
1
MT16HTF6464AG-40E__
MT16HTF6464AY-40E__
MT16HTF6464AG-53E__
MT16HTF6464AY-53E__
MT16HTF12864AG-40E__
2
MT16HTF12864AY-40E__
2
MT16HTF12864AG-53E__
2
MT16HTF12864AY-53E__
2
MT16HTF25664AG-40E__
2
MT16HTF25664AY-40E__
2
MT16HTF25664AG-53E__
2
MT16HTF25664AY-53E__
2
NOTE:
1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory
for current revision codes. Example: MT16HTF12864AG-40EC2.
2. Contact Micron for product availability.
09005aef80f09068
HTF16C64_128_256x64AG_A.fm - Rev. A 11/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
512MB, 1GB, 2GB (x64, DR)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM UDIMM
Table 3:
Pin Assignment
(240-pin DIMM Front)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE0
V
DD
NC/BA2
NC
V
DDQ
A11
A7
V
DD
A5
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A4
V
DDQ
A2
V
DD
V
SS
V
SS
V
DD
NC
V
DD
A10/AP
BA0
V
DDQ
WE#
CAS#
V
DDQ
S1#
ODT1
V
DDQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Table 4:
Pin Assignment
(240-pin DIMM Back)
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
V
SS
DQ28
DQ29
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
DM8
NC
V
SS
NC
NC
V
SS
V
DDQ
CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
181 V
DDQ
211 DM5
182
A3
212
NC
183
A1
213
V
SS
184
V
DD
214 DQ46
185
CK0
215 DQ47
186 CK0# 216
V
SS
187
V
DD
217 DQ52
188
A0
218 DQ53
189
V
DD
219
V
SS
190
BA1
220
CK2
191 V
DDQ
221 CK2#
192 RAS# 222
V
SS
193
S0#
223 DM6
194 V
DDQ
224
NC
195 ODT0 225
V
SS
196
NC/A13
226 DQ54
197
V
DD
227 DQ55
198
V
SS
228
V
SS
199 DQ36 229 DQ60
200 DQ37 230 DQ61
201
V
SS
231
V
SS
202 DM4 232 DM7
203
NC
233
NC
204
V
SS
234
V
SS
205 DQ38 235 DQ62
206 DQ39 236 DQ63
207
V
SS
237
V
SS
208 DQ44
238 V
DDSPD
209 DQ45
239
SA0
210
V
SS
240
SA1
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
CK1
CK1#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
NC
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
Pin 196 is NC for 512MB, or A13 for 1GB and 2GB; pin 54 is NC for 512MB and 1GB, or BA2 for 2GB.
Figure 2: Pin Locations
Front View
U1
U2
U3
U4
U6
U7
U8
U9
U19
PIN 1
PIN 64
PIN 65
PIN 120
Back View
U10
U11
U12
U13
U15
U16
U17
U18
PIN 240
PIN 185
PIN 184
PIN 121
Indicates a VDD or VDDQ pin
Indicates a VSS pin
09005aef80f09068
HTF16C64_128_256x64AG_A.fm - Rev. A 11/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
512MB, 1GB, 2GB (x64, DR)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM UDIMM
Table 5:
PIN NUMBERS
77, 195
Pin Descriptions
SYMBOL
ODT0, ODT1
TYPE
Input
DESCRIPTION
On-Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ0–DQ7, DQS,
DQS#, and DM. The ODT input will be ignored if disabled via the
LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock Enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry, POWER-DOWN exit, output disable, and
for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH
exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_18 input but
will detect a LVCMOS LOW level once V
DD
is applied during first
power-up. After Vref has become stable during the power on
and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh operation
V
REF
must be maintained to this input.
Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when
S# is registered HIGH. S# provides for external rank selection on
systems with multiple ranks. S# is considered part of the
command code.
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank Address Inputs: BA0–BA2 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA2 define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE
command.
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for Read/
Write commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA2) or all
device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE command.
Input Data Mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
137, 138, 185, 186, 220, 221
CK0, CK0#,
CK1, CK1#,
CK2, CK2#
CKE0, CKE1
Input
52, 171
Input
76, 193
S0#, S1#
Input
73, 74, 192
54
(2GB),
71, 190
RAS#, CAS#, WE#
BA0, BA1,
BA2
(2GB)
Input
Input
57, 58, 60, 61, 63, 70, 176,
177, 179, 180, 182, 183, 188,
196
(1GB, 2GB)
A0–A12
(512MB)
A0-A13
(1GB, 2GB)
Input
125, 134, 146, 155, 202, 211,
223, 232
DM0–DM7
Input
09005aef80f09068
HTF16C64_128_256x64AG_A.fm - Rev. A 11/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
PRELIMINARY
512MB, 1GB, 2GB (x64, DR)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM UDIMM
Table 5:
PIN NUMBERS
3, 4, 9, 10, 12, 13, 21, 22, 24,
25, 30, 31, 33, 34, 39, 40, 80,
81, 86, 87, 89, 90, 95, 96, 98,
99, 107, 108, 110, 111, 116,
117, 122, 123, 128, 129, 131,
132, 140, 141, 143, 144, 149,
150, 152, 153, 158, 159, 199,
200, 205, 206, 208, 209, 214,
215, 217, 218, 226, 227, 229,
230, 235, 236
6, 7, 15, 16, 27, 28, 36, 37,
45, 46, 83, 84, 92, 93, 104,
105, 113, 114,
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
I/O
DESCRIPTION
Data Input/Output: Bidirectional data bus.
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
DQS0–DQS7,
DQS0#–DQS7#
120
101, 239, 240
119
SCL
SA0–SA2
SDA
53, 59, 64, 67, 69, 172, 178,
184, 187, 189, 197,
51, 56, 62, 72, 75, 78, 170,
175, 181, 191, 194,
1
2, 5, 8, 11, 14, 17, 20, 23, 26,
29, 32, 35, 38, 41, 44, 47, 50,
65, 66, 79, 82, 85, 88, 91, 94,
97,100, 103, 106, 109,112,
115, 118, 121, 124, 127, 130,
133, 136, 139, 142, 145, 148,
151, 154, 157, 160, 163, 166,
169, 198, 201, 204, 207, 210,
213, 216, 219, 222, 225, 228,
231, 234, 237
238
18, 19, 42, 43, 48, 49, 54
(512MB, 1GB), 55, 68, 76, 77,
102, 125, 126, 134, 135, 146,
147, 155, 156, 161, 162, 164,
165, 167, 168, 171, 173, 174,
196 (512MB), 202, 203, 211,
212, 223, 224, 232, 233
V
DD
V
DD
Q
V
REF
V
SS
Data Strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Input Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Input Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power Supply: +1.8V ±0.1V
Supply DQ Power Supply: +1.8V ±0.1V. Isolated on the device for
improved noise immunity.
Supply SSTL_18 reference voltage.
Supply Ground.
I/O
V
DDSPD
NC
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
—
No Connect: These pins should be left unconnected.
09005aef80f09068
HTF16C64_128_256x64AG_A.fm - Rev. A 11/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
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