DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC1854A
I
2
C BUS-COMPATIBLE US MTS PROCESSING LSI
The
µ
PC1854A is an integrated circuit for US MTS (Multichannel Television Sound) system with the addition of
the I
2
C bus interface. All functions required for US MTS system are incorporated on a single chip.
The
µ
PC1854A allows users to switch modes and adjust filter and separation circuits through the I
2
C bus.
FEATURES
• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, and I
2
C bus
interface incorporated on a single chip
• Mode switching and filter/separation adjustments through the I
2
C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I
2
C bus control)
• Output level: 1.4 V
p-p
(with L+R signals, 100% modulation)
APPLICATIONS
• TV sets and VCRs for north America
ORDERING INFORMATION
Part Number
Package
28-pin plastic SDIP (10.16 mm (400))
28-pin plastic SOP (9.53 mm (375))
µ
PC1854ACT
µ
PC1854AGT
The
µ
PC1854A is available only to licensees of THAT Corporation.
For information, please call: (508) 229-2500 (U.S.A.), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S12816EJ3V0DS00 (3rd edition)
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µ
PC1854A
SYSTEM BLOCK DIAGRAM
Tuner
IF processing
C, Y, and deflecting
signal processing
Chroma output
CRT
DTS interface
Vertical output
µ
PC1854A
L
US MTS
processing
R
Tuning
microcontroller
SDA
Surround signal
processing
Power amplifier
SCL
Remote
controller
receive amp.
PIN photodiode
2
Data Sheet S12816EJ3V0DS00
µ
PC1854A
BLOCK DIAGRAM
9V
V
CC
1
De-
emphasis
Offset
Absorption
28
MOA
1
µ
F
+
LOT
10
µ
F
+
ROT
10
µ
F
+
Pilot
Canceller
Mode
Selector
Offset
Absorption
NOT
10
µ
F
+
VOA
1
µ
F
+
WTI
10
µ
F
+
STI
3.3
µ
F
+
Timing
Current
2f
H
Trap
Spectral
RMS
Filter
D/A
22
µ
F
+
VRE
2
1/2 V
CC
L–R
AM
Demodulator
L+R
LPF
Matrix
Pilot
Discrimination
Phase
Comparator
Stereo
VCO
27
PD1
0.1
µ
F
PD2
3
26
4
1/4
1/2
ST VCO
25
1 kΩ
4.7
µ
F
+
+
φ
D1
1
µ
F
5
Stereo
Phase
Comparator
6
D/A
D/A
ST VCO
SAP VCO
Filter
Stereo
LPF
ST/SAP
SW
Wide-
Band
VCA
Wide-
Band
RMS
Filter
D/A
24
φ
D2
2.2
µ
F
COM
+
0.1
µ
F
SOA
+
0.047
µ
F
SDT
23
Wide-
Band
RMS
22
7
Input
Attenuator
LPF
Filter
f
H
Trap
8
Offset
Absorption
Noise
BPF
SAP
BPF
21
ITI
1.6 kΩ 15 kΩ
WRB
1
µ
F
9
20
Spectral
RMS
19
5.1 kΩ +
SRB
3 kΩ
dO
1
µ
F
+
1
µ
F
+
DGND
0.47
µ
F
+
NDT
68 kΩ
SOT
10
Noise
Detector
SAP
Detector
Phase
Detector
11
SAP
LPF
Loop
Filter
0.1
µ
F
External
dbx NR
SI
12
408 Hz
LPF
Variable
Emphasis
2.19 kHz
LPF
Offset
Absorption
18
SAP
VCO
D/A
17
ESA
13
1/2
SAP VCO
Filter
Adjuster
D/A
16
I
2
C Bus
Interface
15
SCL
AGND
14
SDA
Remark
Use the following for external parts.
Resistor : Metal film resistor (±1 %) for an ITI pin (pin 21). Unless otherwise specified;
±5
%
Capacitor : Tantalum capacitor (±10 %) for STI and WTI pins (pins 22 and 23). Unless otherwise
specified;
±20
%
Data Sheet S12816EJ3V0DS00
3
µ
PC1854A
PIN CONFIGURATION (Top View)
28-pin plastic SDIP (10.16 mm (400))
•
µ
PC1854ACT
28-pin plastic SOP (9.53 mm (375))
•
µ
PC1854AGT
Power (9 V)
1/2 V
CC
Filter
Pilot Discrimination Filter 1
Pilot Discrimination Filter 2
Phase Comparator Filter 1
Phase Comparator Filter 2
Composite Signal Input
SAP Offset Absorption
SAP Discrimination Filter
Noise Detection Filter
SAP Single Output
SAP Single Input
External SAP Input
Analog GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V
CC
VRE
PD1
PD2
φ
D1
φ
D2
MOA
LOT
ROT
NOT
VOA
WTI
STI
ITI
WRB
SRB
dO
DGND
SCL
SDA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Monaural Offset Absorption
L-channel Output
R-channel Output
Normal Output
VCA Offset Absorption
Wide-Band RMS Timing
Spectral RMS Timing
Timing Current Setting
Wide-Band RMS Offset Absorption
Spectral RMS Offset Absorption
Variable Emphasis Offset Absorption
Digital GND (for I
2
C bus)
SCL (for I
2
C bus)
SDA (for I
2
C bus)
COM
SOA
SDT
NDT
SOT
SI
ESA
AGND
4
Data Sheet S12816EJ3V0DS00
µ
PC1854A
CONTENTS
1.
2.
PIN EQUIVALENT CIRCUITS .............................................................................................................................. 6
BLOCK FUNCTIONS .......................................................................................................................................... 13
2.1
2.2
2.3
2.4
Stereo Demodulation Block ..................................................................................................................... 14
SAP Demodulation Block ........................................................................................................................ 15
dbx Noise Reduction Block ..................................................................................................................... 16
Matrix Block .............................................................................................................................................. 17
3.
I
2
C BUS INTERFACE ......................................................................................................................................... 18
3.1
3.2
Data Transfer ........................................................................................................................................... 19
Data Transfer Format .............................................................................................................................. 20
4.
I
2
C BUS COMMANDS ........................................................................................................................................ 22
4.1
4.2
4.3
4.4
Subaddress List ....................................................................................................................................... 22
Setting Procedure .................................................................................................................................... 23
Explanation of Write Register .................................................................................................................. 25
Explanation of Read Register ................................................................................................................. 28
5.
MODE MATRIX ................................................................................................................................................... 30
5.1
5.2
L-, R-Channel Output (LOT, ROT pins) Matrix ....................................................................................... 30
Normal Output (NOT pin) Matrix ............................................................................................................. 31
6.
USAGE CAUTIONS ............................................................................................................................................ 32
6.1
6.2
6.3
6.4
6.5
6.6
Caution on Shock Noise Reduction ........................................................................................................ 32
Supply Voltage ......................................................................................................................................... 32
Impedance of Input and Output Pins ...................................................................................................... 32
Drive Capability of Output Pins ............................................................................................................... 32
Caution on External Components ........................................................................................................... 33
Change of Electrical Characteristics by External Components ............................................................. 33
7.
8.
9.
ELECTRICAL SPECIFICATIONS ...................................................................................................................... 34
MEASURING CIRCUIT ....................................................................................................................................... 44
PACKAGE DRAWINGS ..................................................................................................................................... 45
10. RECOMMENDED SOLDERING CONDITIONS ................................................................................................ 47
Data Sheet S12816EJ3V0DS00
5
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