Features
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High-performance, High-density, Electrically-erasable Programmable Logic Device
Fully Connected Logic Array with 416 Product Terms
10 ns Maximum Pin-to-pin Delay for 5V Operation
Low-power Edge-sensing “L” Option with <1 mA Standby Current
24 Flexible Output Macrocells
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
D- or T-type Flip-flops
Product Term or Direct Input Pin Clocking
Registered or Combinatorial Internal Feedback
Backward Compatible with ATV2500B/BQL and ATV2500H/L Software
Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
44-lead Surface Mount Package
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ATF2500C
CPLD Family
Datasheet
ATF2500C
ATF2500CL
ATF2500CQ
ATF2500CQL
Preliminary
Block Diagram
Description
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully
connected logic array and flexible macrocell structure, high gate utilization is easily
obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) pro-
grammable logic device (PLD) that utilizes Atmel’s proven electrically-erasable
technology.
Pin Configurations
Pin Name
IN
CLK/IN
I/O
I/O 0,2,4...
I/O 1,3,5...
GND
VCC
Function
Logic Inputs
Pin Clock and Input
Bi-directional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
+5V Supply
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC/JLCC
I/O1
I/O0
GND
IN
IN
CLK/IN
IN
IN
IN
IN
I/O6
6
5
4
3
2
1
44
43
42
41
40
I/O12
IN
IN
IN
IN
IN
IN
IN
IN
I/O18
I/O19
18
19
20
21
22
23
24
25
26
27
28
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
Note:
For
ATF2500CQ
and
ATF2500CQL
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required.
Rev. 0777G–12/01
1
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-
cell’s three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-
viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-
flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
The Atmel-unique “L” low-power feature is an edge-sensing option that is now field program-
mable for the ATF2500C family. The “L” feature utilizes Atmel-patented Input Transition
Detection (ITD) circuitry and is activated by selecting the “L” option from the program menu.
Using the
ATF2500C
Family’s Many
Advanced
Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
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Fully Connected Logic Array –
Each array input is always available to every product
term. This makes logic placement a breeze.
Selectable D- and T-Type Registers –
Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
Buried Combinatorial Feedback –
Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking –
Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
A Total of 48 Registers –
The ATF2500C provides two flip-flops per macrocell – a total of
48. Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths –
Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.
Combinable Sum Terms –
Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with
no
speed penalty.
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2
ATF2500C Family
0777G–12/01
ATF2500C Family
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from V
CC
crossing V
RST
, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how V
CC
actually rises
in the system, the following conditions are required:
1. The V
CC
rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3. The clock pin, and any signals from which clock terms are derived, must remain stable
during t
PR
.
Parameter
t
PR
V
RST
Description
Power-up Reset Time
Power-up Reset Voltage
Typ
600
3.8
Max
1000
4.5
Units
ns
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
V
IH
/V
IL
V
IH
/V
IL
V
IH
/V
IL
V
IH
/V
IL
Q Select Pin
State
Low
High
Low
High
Even/Odd
Select
Low
Low
High
High
Even Q1 State
after Cycle
High/Low
X
X
X
Even Q2 State
after Cycle
X
High/Low
X
X
Odd Q1 State
after Cycle
X
X
High/Low
X
Odd Q2 State
after Cycle
X
X
X
High/Low
3
0777G–12/01
Preload and
Observability of
Registered
Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
IH
level on the odd I/O pins will force the
appropriate register high; a V
IL
will force it low, independent of the polarity or other configura-
tion bit settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.
Programming
Software
Support
All family members of the ATF2500C can be designed with Atmel-Synario
™
and Atmel-Win-
CUPL
™
. ProChip
™
designer support will be available Q102.
Additionally, the ATF2500C may be programmed to perform the ATV2500H/Ls functional sub-
set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In
this case, the ATF2500C becomes a direct replacement or speed upgrade for the
ATV2500H/L. The ATF2500CQ/CQL are direct replacements for the ATV2500BQ/BQL and
the AT2500H/L, including the lack of extra grounds on P4 and P26.
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
Security Fuse
Usage
Input and I/O
Pull-ups
All ATF2500C family members have programmable internal input and I/O pinkeeper circuits.
The default condition, including when using the AT2500CQ/CQL family to replace the
AT2500BQ/BQL or AT2500H/L, is that the pinkeepers are not activated.
When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states.
Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).
4
ATF2500C Family
0777G–12/01
ATF2500C Family
Input Diagram
I/O Diagram
INPUT
Functional
Logic Diagram
Description
The ATF2500C functional logic diagram describes the interconnections between the input,
feedback pins and logic cells. All interconnections are routed through the single global bus.
The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into
three sum terms, which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.
The 14 dedicated inputs and their complements use the numbered positions in the global bus
as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2
(1)
true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by
these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Note:
1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.
5
0777G–12/01
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