DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC3211GR
AGC AMPLIFIER FOR DIGITAL CATV RETURN PASS
DESCRIPTION
The
µ
PC3211GR is a silicon monolithic integrated circuit designed as AGC amplifier for digital CATV systems. This
IC is the AGC amplifier with 55 dB gain control range which is packaged in 20-pin SSOP. The device is able to use
for digital QPSK system, therefore it contributes to make design of transmission system simplicity.
FEATURES
• Wide gain control range
• Low distortion
• Supply Voltage
55 dB TYP.
IM
3
= 57 dBc TYP. @P
out
=
−10
dBm
IM
2
= 44 dBc TYP. @P
out
=
−10
dBm
9V
• Packaged in 20-pin SSOP suitable for high-density surface mount.
ORDERING INFORMATION
Part Number
Package
20-pin plastic SSOP (225 mil)
Supplying Form
Embossed tape 12 mm wide.
Pin 1 indicates pull-out direction of tape.
Qty 2.5 kp/reel
µ
PC3211GR-E1
To order evaluation samples, please contact your local NEC office. (Part number for sample order:
µ
PC3211GR)
Caution electro-static sensitive device
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P13564EJ3V0DS00 (3rd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1998, 1999
µ
PC3211GR
INTERNAL BLOCK DIAGRAM AND PIN CONFIGURATION (TOP VIEW)
BY2
VAGC
GND2A
GND2B
V
CC
1
V
CC
2
GND2C
GND2D
GND2E
BY3
1
2
3
4
5
6
7
8
9
10
Cont.
20
19
18
17
16
15
14
13
12
11
BY1
AGC IN1
GND1A
AGC IN2
GND1B
PSAVE
PA_BIAS
GND3
OUT1
OUT2
REG
TYPICAL APPLICATION
LPF
RF IN
50-750 MHz
RF Return
5-42 MHz
HPF
µ
PC2799GR
1st IF
SAW
µ
PC1686GV
2nd IF
SAW
µ
PC2798GR
DC-10 MHz
A/D
Video Amplifier
QAM
Demo.
&FEC
DUAL
PLL
µ
PC3211GR
Bias
Digital
QPSK
Modulator
LPF
2
Data Sheet P13564EJ3V0DS00
µ
PC3211GR
PIN FUNCTIONS
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
Pin
Name
BY2
VAGC
GND2A
GND2B
V
cc
1
V
cc
2
GND2C
GND2D
GND2E
BY3
OUT2
Pin
Voltage
TYP. (V)
–
0 to 3
0.0
0.0
9.0
9.0
0.0
0.0
0.0
1.64
6.9
Bypass pin of regulator block.
Signal output pins.
This pins feature low-impedance
because of its emitter-follower output
port.
The pin that is not used should be
grounded through 50 ohm resistor.
6
Function and Explanation
Non Connection pin.
This pin should be opened.
Automatic gain control pin.
Ground pins of differential amplifier.
Equivalent Circuit
Power supply pin of AGC amplifier
block.
Power supply pin of differential
amplifier and output block.
Ground pins of differential amplifier.
11
REG
12
12
OUT1
6.9
13
14
GND3
PA_BIAS
0.0
2.45
Ground pin of output block.
This is the pin to feed base bias in
case of connection to transistor as
power amplifier.
5
V
CC
(9 V)
15
5 kΩ
14
15
Psave
9.0
(+5 kΩ)
Power-save pin.
V
cc
: ON
GND : SLEEP
The 5 kΩ resistor should be
connected between 15 pin and V
cc
.
Ground pin of AGC amplifier block.
16
18
17
GND1B
GND1A
AGC IN2
0.0
0.0
2.43
Signal input pin.
In the case of single input, 17 or 19
pin should be grounded through
capacitor.
19
5
19
AGC IN1
2.43
17
20
BY1
–
Non Connection pin.
This pin should be opened.
Data Sheet P13564EJ3V0DS00
3
µ
PC3211GR
ABSOLUTE MAXIMUM RATINGS (T
A
= +25°C unless otherwise specified)
Parameter
Supply Voltage
Power-save Voltage
AGC Voltage
Power Dissipation
Operating Ambient Temperature
Storage Temperature
Maximum Input Level
Symbol
V
CC
V (Psave)
V
AGC
P
D
T
A
T
stg
P
in
(MAX)
T
A
= +75°C
Note 2
Note 1
Test Condition
Rating
11.0
11.0
3.6
500
−40
to +75
−55
to +150
+5
Unit
V
V
V
mW
°C
°C
dBm
Notes 1.
Bias to 15 pin through 5 kΩ resistor.
2.
Mounted on 50 mm
×
50 mm
×
1.6 mm double epoxy glass board.
RECOMMENDED OPERATING RANGE
Parameter
Supply Voltage
Power-save Voltage
AGC Control Voltage
Operating Ambient Temperature
Input Frequency
Maximum Input Level
Symbol
V
CC
V (Psave)
V
AGC
T
A
f
in
P
in
(MAX)
Note
Test Condition
MIN.
8.0
0
0
−40
5
–
TYP.
9.0
–
–
+25
–
–
MAX.
10.0
10.0
3.3
+75
100
0
Unit
V
V
V
°C
MHz
dBm
Note
Bias to 15 pin through 5 kΩ resistor.
ELECTRICAL CHARACTERISTICS (T
A
= +25°C, V
CC
= 9 V, V
AGC
= 0 V, V (Psave) = 9 V (+5 kΩ), unless otherwise
Ω
specified)
Parameter
Circuit Current 1
Maximum Gain
Gain Control Range
Symbol
I
CC
1
G
MAX
GCR
Test Conditions
No input signal
Note 1
MIN.
29
14
47
TYP.
38
16
55
MAX.
51
18
–
Unit
mA
dB
dB
f
in
= 65 MHz, P
in
=
−20
dBm
Note 2
f
in
= 65 MHz, P
in
=
−20
dBm,
V
AGC
= 0 to 3 V
Note 2
f
in
= 65 MHz, P
in
=
−20
dBm,
V (Psave) = 0 V (+5 kΩ)
Note 2
f
in
1 = 65 MHz, f
in
2 = 66.8 MHz,
P
out
=
−10
dBm
Note 2
f
in
1 = 65 MHz, f
in
2 = 66.8 MHz,
P
out
=
−10
dBm
Note 2
Isolation at sleep mode
Isol
60
65
–
dB
2nd order intermodulation distortion
IM
2
–
–44
–40
dBc
3rd order intermodulation distortion
IM
3
–
–57
–50
dBc
Notes 1.
By measurement circuit 1
2.
By measurement circuit 2
4
Data Sheet P13564EJ3V0DS00
µ
PC3211GR
STANDARD CHARACTERISTICS (T
A
= +25°C, V
CC
= 9 V, V
AGC
= 0 V, V (Psave) = 9 V (+5 kΩ), unless otherwise specified)
Ω
Parameter
Maximum Output Power
Circuit Current at Power-save mode
Symbol
P
O (sat)
I
CC
(P/S)
Test Conditions
f
in
= 65 MHz, P
in
=
−5
dBm
Note 1
Reference Value
+5
3
Unit
dBm
mA
No input signal, V (Psave) = 0 V (+5 kΩ)
Note 2
f
in
= 65 MHz
Note 3
Noise Figure
Output Intercept Point
Gain Flatness
NF
OIP
3
G
flat
10
+16
±0.1
dB
dBm
dB
f
in
1 = 65 MHz, f
in
2 = 66.8 MHz
Note 1
f
in
= 5 to 100 MHz, 6 MHz Band width
P
in
=
−20
dBm
Note 1
No input signal, V
AGC
= 3 V
f
in
= 65 MHz,
V (Psave) = 0
→
9 V (+5 kΩ)
f
in
= 65 MHz,
V (Psave) = 9
→
0 V (+5 kΩ)
Note 2
Circuit Current 2
ON Time
I
CC
2
t
ON
43
200
mA
µ
sec
msec
Note 4
1.7
Note 4
OFF Time
t
OFF
Notes 1.
By measurement circuit 2
2.
By measurement circuit 1
3.
By measurement circuit 3
4.
By measurement circuit 4
Data Sheet P13564EJ3V0DS00
5
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