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UPC4091C

产品描述OP-AMP, PDIP8
产品类别配件   
文件大小54KB,共12页
制造商NEC ( Renesas )
官网地址https://www2.renesas.cn/zh-cn/
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UPC4091C概述

OP-AMP, PDIP8

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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC4091
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The
µ
PC4091 operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable AC
operating characteristics. NEC's unique high-speed PNP transistor (f
T
= 300 MHz) in the output stage solves the
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage
produces excellent offset voltage and temperature drift characteristics.
FEATURES
• Stable operation with 10000 pF capacitive load
• Low input offset voltage and offset voltage null
capability
±2.5
mV (MAX.)
±7
µ
V/°C (TYP.) temperature drift
• Very low input bias and offset currents
• Low noise : e
n
= 19 nV/
√Hz
(TYP.)
• Output short circuit protection
• High input impedance ... J-FET Input Stage
• Internal frequency compensation
• High slew rate: 15 V/
µ
s (TYP.)
ORDERING INFORMATION
Part Number
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
µ
PC4091C
µ
PC4091G2
EQUIVALENT CIRCUIT
V
+
(7)
Q
9
(2)
I
I
Q
1
I
N
(3)
Q
5
(1)
OFFSET
NULL
Q
3
Q
4
(5)
OFFSET
NULL
Q
2
C
1
D
1
Q
10
Q
7
(6)
HIGH SPEED
PNP
Q
6
OUT
PIN CONFIGURATION
(Top View)
µ
PC4091C, 4091G2
OFFSET
1
NULL
I
I
2
– +
8 NC
7 V
+
I
N
3
6 OUT
OFFSET
5 NULL
V
Q
8
(4)
4
TRIMMED
V
Remark
NC : No Connection
The information in this document is subject to change without notice.
Document No. G13904EJ1V0DS00 (1st edition)
Date Published November 1998 N CP(K)
Printed in Japan
©
1998

UPC4091C相似产品对比

UPC4091C UPC4091G2 UPC4091
描述 OP-AMP, PDIP8 OP-AMP, PDSO8 OP-AMP, PDSO8

 
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