DATA SHEET
MOS INTEGRATED CIRCUIT
PD16312
1/4- to 1/11-DUTY FIP
TM
(VFD) CONTROLLER/DRIVER
The
PD16312 is a FIP (fluorescent Indicator Panel, or Vacuum Fluorescent Display) controller/driver that is
driven on a 1/4- to 1/11 duty factor. It consists of 11 segment output lines, 6 grid output lines, 5 segment/grid output
drive lines, a display memory, a control circuit, and a key scan circuit. Serial data is input to the
PD16312 through a
three-line serial interface. This FIP controller/driver is ideal as a peripheral device for a single-chip microcomputer.
FEATURES
• Multiple display modes (11-segment & 11-digit to 16-segment & 4-digit)
• Key scanning (6
4 matrix)
• Dimming circuit (eight steps)
• High-voltage output (V
DD
35 V max).
• LED ports (4 chs., 20 mA max).
• General-purpose input port (4 bits)
• No external resistors necessary for driver outputs (P-ch open-drain + pull-down resistor output)
• Serial interface (CLK, STB, D
IN
, D
OUT
)
ORDERING INFORMATION
Part Number
Package
44-pin plastic QFP ( 10)
PD16312GB-3B4
Document No. IC-3307 (1st edition)
Date Published March 1997 P
Printed in Japan
©
1993
PD16312
BLOCK DIAGRAM
Command decoder
Dimming circuit
D
IN
D
OUT
Serial I/F
CLK
STB
V
DD
R
OSC
Timing generator key scan
Data
selector
5
Seg
1
16-bit 16
output
latch
5
11
Seg-
ment
driver
Seg
11
Display memeory
16 bits
×
11 words
Multip lexed
diver
Seg
12
/Grid
11
Seg
16
/Grid
7
Key data memory (4
×
6)
Key
1
to
Key
4
11-bit
shift
register
11
5
Grid
1
6
Grid
driver
Grid
6
4
SW
1
to
SW
4
4-bit latch
4
4-bit
latch
LED
1
LED
4
Key data memory (4
×
6)
V
DD
(+5 V)
V
SS
V
EE
(0 V) (−30 V)
2
PD16312
PIN CONFIGURATION (Top View)
LED
1
LED
2
LED
3
LED
4
Grid
1
Grid
2
Grid
3
35
Grid
4
34
33
32
31
30
29
28
27
26
25
24
23
OSC
44
43
42
41
40
39
38
V
DD
V
SS
37
SW
1
SW
2
SW
3
SW
4
D
OUT
D
IN
V
SS
CLK
STB
KEY
1
KEY
2
1
2
3
4
5
6
7
8
9
36
Grid
5
Grid
6
Seg
16
/Grid
7
Seg
15
/Grid
8
Seg
14
/Grid
9
Seg
13
/Grid
10
V
EE
Seg
12
/Grid
11
Seg
11
Seg
10
Seg
9
10
11
12
13
14
15
16
17
18
19
20
21
Seg
7
Seg
1
/KS
1
Seg
2
/KS
2
Seg
3
/KS
3
Seg
4
/KS
4
Seg
5
/KS
5
Seg
6
/KS
6
KEY
3
KEY
4
Use all power pins.
Seg
8
V
DD
22
3
PD16312
Pin Function
Symbol
D
IN
Pin Name
Data input
Pin No
6
Description
Input serial data at rising edge of shift clock, starting from the low
order bit.
Output serial data at the falling edge of the shift clock, starting
from low order bit. This is N-ch open-drain output pin.
Initializes serial interface at the rising or falling edge of the
PD16312. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While
command data is processed, current processing is stopped, and
the serial interface is initialized. While STB is high, CLK is
ignored.
Reads serial data at the rising edge, and outputs data at the
falling edge.
Connect resistor to this pin to determine the oscillation frequency
to this pin.
Segment output pins (Dual function as key source)
D
OUT
Data output
5
STB
Strobe
9
CLK
Clock input
8
OSC
Oscillator pin
44
Seg
1
/KS
1
to
Seg
6
/KS
6
Seg
7
to Seg
11
High-voltage output
15 to 20
High-voltage output
(segment)
High-voltage output (grid)
High-voltage output
(segment/grid)
LED output
Key data input
Switch input
Logic power
Logic ground
Pull-down level
21 to 25
Segment output pins
Grid
1
to Grid
6
Seg
12
/Grid
11
to
Seg
16
/Grid
7
LED
1
to LED
4
KEY
1
to KEY
4
SW
1
to SW
4
V
DD
V
SS
V
EE
37 to 32
26, 28 to 31
Grid output pins
These pins are selectable for segment or grid driving.
42 to 39
10 to 13
1 to 4
14, 38
7, 43
27
CMOS output. +20 mA max.
Data input to these pins is latched at the end of the display cycle.
These pins constitute a 4-bit general-purpose input port.
5 V
10 %
Connect this pin to system GND.
V
DD
35 V max.
4
PD16312
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an external device to the
PD16312 through the serial interface,
and is assigned addresses as follows, in 8 bits unit:
Seg
1
00H
L
02H
L
04H
L
06H
L
08H
L
0AH
L
0CH
L
0EH
L
10H
L
12H
L
14H
L
Seg
4
00H
U
02H
U
04H
U
06H
U
08H
U
0AH
U
0CH
U
0EH
U
10H
U
12H
U
14H
U
Seg
8
Seg
12
01H
L
03H
L
05H
L
07H
L
09H
L
0BH
L
0DH
L
0FH
L
11H
L
13H
L
15H
L
Seg
16
01H
U
03H
U
05H
U
07H
U
09H
U
0BH
U
0DH
U
0FH
U
11H
U
13H
U
15H
U
DIG
1
DIG
2
DIG
3
DIG
4
DIG
5
DIG
6
DIG
7
DIG
8
DIG
9
DIG
10
DIG
11
b
0
xxH
L
b
3
b
4
xxH
U
b
7
Lower 4 bits
Higher 4 bits
5
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