DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16633B
312 OUTPUT TFT-LCD SORCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALES)
The
µ
PD16633B is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values
γ
-corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as 9.8 V
P-P
, level inversion operation of the LCD’s common electrode is
rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source
driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 3.0
V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 9.8 V
P-P
min. (@V
DD2
= 10.0 V)
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V)
• 312 outputs
• Apply for only dot inversion
• Display data inversion function (POL2 terminal.)
• Single bank arrangement is possible (loaded with slim TCP)
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
µ
PD16633BN-×××
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
Document No. S13214EJ2V0DS00 (2nd edition)
Date Published July 1998 N CP(K)
Printed in Japan
©
1998
µ
PD16633B
1. BLOCK DIAGRAM
STHR
R/L
CLK
STB
STHL
V
DD1
V
SS1
C
51
C
52
50-bit bidirectional shift register
C
1
C
2
D
00
-
05
D
10
-
15
D
20
-
25
D
30
-
35
D
40
-
45
D
50
-
55
POL2
Data register
POL
Latch
V
DD2
Level shifter
V
SS2
V
0
-V
9
D/A converter
Voltage follower output
S
1
S
2
S
3
S
312
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
S
2
S
311
S
312
V
0
V
4
V
5
V
9
Multi-
plexer
5
6-bit D/A converter
5
POL
2
µ
PD16633B
3. PIN CONFIGURATION (
µ
PD16633BN-××× (Copper Plated surface)
×××)
×××
V
SS2
V
DD2
V
SS1
R/L
POL
STB
D
55
D
54
D
53
D
52
D
51
D
50
D
45
D
44
D
43
D
42
D
41
D
40
D
35
D
34
D
33
D
32
D
31
STHL
V
9
V
8
V
7
V
6
V
5
V
4
V
3
V
2
V
1
V
0
CLK
STHR
D
30
D
25
D
24
D
23
D
22
D
21
D
20
D
15
D
14
D
13
D
12
D
11
D
10
D
05
D
04
D
03
D
02
D
01
D
00
POL2
TEST
V
DD1
V
DD2
V
SS2
S
312
S
311
S
310
S
309
S
4
S
3
S
2
S
1
Caution This figure does not specify the TCP package.
3
µ
PD16633B
4. PIN FUNCTIONS
Pin Symbol
S
1
to S
312
D
00
to D
05
D
10
to D
15
D
20
to D
25
D
30
to D
35
D
40
to D
45
D
50
to D
55
R/L
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade. The shift directions of the shift registers are as follows.
R/L = H : STHR input, S
1
→S
312
, STHL output
R/L = L : STHL input, S
312
→S
1
, STHR output
R/L = H : Becomes the start pulse input pin.
R/L = L : Becomes the start pulse output pin.
R/L = H : Becomes the start pulse output pin.
R/L = L : Becomes the start pulse input pin.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 52nd clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-level driver. The initial-level driver’s 52nd clock becomes
valid as the next-level driver’s start pulse is input. If 54th clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It
is necessary to ensure input of one pulse per horizontal period.
POL = L ; The S
2n–1
output uses V
0
to V
4
as the reference supply;
The S
2n
output uses V
5
to V
9
as the reference supply.
POL = H; The S
2n–1
output uses V
5
to V
9
as the reference supply;
The S
2n
output uses V
0
to V
4
as the reference supply.
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted.
Input the
γ
-corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
V
DD2
> V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
> V
SS2
TEST = H or Open: Standard mode
TEST = L: Test mode
Please input “H” level.
3.3 V
±
0.3 V
10.0 V to 13.5 V
Grounding
Grounding
Pin Name
Driver output
Display data input
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
by 6 dots (2 pixels).
D
X0
: LSB, D
X5
: MSB
STHR
Right shift start pulse
input/output
Left shift start pulse
input/output
Shift clock input
STHL
CLK
STB
Latch input
POL
Polarity input
POL2
Data inversion
V
0
to V
9
γ
-corrected power
supplies
TEST
Test pin
V
DD1
V
DD2
V
SS1
V
SS2
Logic power supply
Driver power supply
Logic ground
Driver ground
4
µ
PD16633B
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
to V
9
in that order. Reverse
this sequence to shut down. (Simultaneous power application to V
DD2
and V
0
to V
9
is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.47
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter, insertion of
a bypass capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power supply
terminals (V
0
, V
1
, V
2
, ···, V
9
) and V
SS2
.
5
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