DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD16681A
LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1
AND JIS LEVEL 2 KANJI SETS
DESCRIPTION
The
µ
PD16681A is a single-chip controller driver that can display Japanese text; including JIS Level 1 kanji, JIS
Level 2 kanji, hiragana, and katakana. Each chip can display up to four lines containing up to eight full width
characters (11 x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96
pictographs.
FEATURES
•
LCD controller/driver for dot matrix display of JIS Level 1 and JIS Level 2 kanji sets
•
On-chip ROM for character generation
−JIS
Level 1 + Level 2 kanji (11 x 12 dots) : 6,355 characters
−JIS
non-kanji characters (11 x 12 dots) : 453 characters
−Other
characters (symbols, etc.) (11 x 12 dots): 256 characters
−Half
width alphanumeric characters (5 x 12 dots) : 192 characters
•
On-chip RAM for character generation
−8
types (12 x 13 dots)
•
On-chip boost circuit : switchable between 3x and 4x modes
•
RAM for pictograph data displays : 96 bits
•
Outputs : 96 segments, 52 commons
•
Duty settings : 1/39 or 1/52
•
Switchable data inputs : serial or 8-bit parallel
•
On-chip divider resistor
•
Selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias)
•
On-chip oscillation circuit
ORDERING INFORMATION
Part number
Package
Wafer
Chip (COG compliant)
ROM code
Standard
Standard
µ
PD16681A-001
µ
PD16681AP-001
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S14207EJ2V0DS00 (2nd edition)
Date Published March 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1999,2000
µ
PD16681A
1. BLOCK DIAGRAM
OSC
OUT
OSC
IN
/RESET
Oscillation Circuit
SEG
INV
COM
INV
V
DD
V
LCD
V
SS
Index
Register
Control
Register
Common
Driver
Display Data RAM
COM
1
to COM
51
PCOM
1
,PCOM
2
Timing Generator
OSC
BRI
WS
STB
E/SCK
D
0
/DATA
D
1
to D
7
8
TEST
OUT
I/O
Buffer
RAM Address
Counter
8
96 bits
Shift
Register
96 bits
Latch
Circuit
Segment
Driver
SEG
1
to SEG
96
RAM Data
Register
8
8
8
4
8
3
Address Formation Circuit
12
Full-width
Character
Generator
ROM
7
Half-width
Character
Generator
ROM
Pictograph
Data RAM
Character
Generator
RAM
6
6
6
6
Display Attribute Control Circuit
DA
CHA
D/A
Converter
Cursor Control
Circuit
DC/DC
Converter
OP Amp.
LCD Voltage Generator
6
Parallel/Serial Conversion Circuit
Smooth Scroll Control Circuit
C
1+
, C
1
−
C
2+
, C
2
C
3+
, C
3
−
V
EXT
−
AMP
IN(+)
AMP
IN(−)
AMP
CHA
V
LC1
V
LC2
V
LC3
V
LCBS1
V
LCBS2
V
LCBS3
V
LC4
V
LC5
AMP
OUT
Remark
/xxx indicates active low signals.
2
Data Sheet S14207EJ2V0DS00
µ
PD16681A
3. PIN FUNCTIONS
3.1 Power Supply System Pins
Pin Symbol
V
DD
Pin Name
Logic power supply pin
Boost circuit power supply
pin
V
SS
Logic ground
Driver ground
V
LCD
Driver power supply pins
29-31
−
Power supply pins for driver. Output pin for internal boost circuit.
Connect a 1-
µ
F capacitor between these pins and the V
SS
pins
for boosting.
If not using the internal boost circuit, a direct driver power supply
can be input.
V
LC1
- V
LC5
Reference power supply
pins for driver
14-28
−
These are reference power supply pins for the LCD driver.
Leave these pins open if an internal bias has been selected.
Connect a capacitor to ground.
When selecting an internal bias, the bias value can be changed
connecting these pins outside of the IC.
These are capacitor connection pins for the boost circuit.
Connect a 1-
µ
F capacitor.
55-59
−
Ground pins for logic and driver circuit
Pad No.
50-54
I/O
−
Description
Power supply pins for logic and boost circuit
V
LCBS1
- V
LCBS3
Bias value setting pins
C
1
, C
1
C
2
, C
2
C
3
, C
3
+
+
+
-
-
-
2-7
32-49
−
−
Capacitor connection pins
Data Sheet S14207EJ2V0DS00
5
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