CN8478/74A/72A/71A
Multichannel Synchronous Communications
Controller (MUSYCC™)
Data Sheet
28478-DSH-002-D
Mindspeed Technologies
®
Preliminary Information / Mindspeed Proprietary and Confidential
October 2006
Ordering Information
Ordering Number
28475-17
28476-17
28477-17
28478-17
28478G-17*
28475-18
28476-18
28477-18
28478-18
28478G-18*
Version
32-Channel
64-Channel
128-Channel
256-Channel
256-Channel
32-Channel
64-Channel
128-Channel
256-Channel
256-Channel
Package
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
RoHS-Compliant
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
208-Pin Plastic Ball Grid Array
RoHS-Compliant
Temperature Range
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
–40 °C to +85 °C
*The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information.
Revision History
Revision
D
B
Level
October
Advance
Date
June 2006
March 2005
Description
• RoHS compliant information added.
• Changed M66EN description.
• Added internal pulldown footnote (Table
1-4).
• Added footnote indications to M66EN, TM[0], TM[1], TM[2], TDI, TMS, and
TRST.
• Changed ordering information
Document No. changed to conform with Mindspeed document numbering system
500183A. Initial document number was 100660A. Converted to Mindspeed format
and logo.
A
Advance
January 2002
• Revised the description of M66EN pin in the Hardware Signal Description
Table
• Revised the description of MSKOOF = 1 in Group Configuration Descriptor
• Added explanation for port mode settings in
Section 4.5—Channelized
Port
Mode
• Changed the minimal MAXFRMx value from 3 to 1 in the Message Length
Descriptor
• Added Electrical Operating Characteristics Table for 66 MHz PCI clock
• Added new paramter entries "Supply Current" and "5-V Tolerant Leakage
Current" to the Electrical Operating Characterics Table for 33 MHz PCI clock.
• Updated the Tsu(ptp) value in PCI I/O Timing Parameters Table for 33 MHz
PCI clock.
• Updated Tval, Tval(ptp), Ton, Toff, Tds, and Tdh values in PCI I/O Timing
Parameters Table for 66 MHz PCI clock.
28478-DSH-002-D
Mindspeed Technologies
®
Preliminary Information / Mindspeed Proprietary and Confidential
ii
CN8478/74A/72A/71A
Distinguishing Features
256-, 128-, 64-, or 32-channel HDLC
controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
SS7 support
8, 4, 2, or 1 independent serial interfaces
which support
T1/E1 data streams
DC to 8.192 Mbps TDM busses
Configurable logical channels
Standard DS0 (56, 64 kbps)
Hyperchannel (Nx64)
Subchannel (Nx8)
Per-channel protocol mode selection
16-bit FCS mode
32-bit FCS mode
SS7 mode (16-bit FCS)
Transparent mode (unformatted data)
Per-channel DMA buffer management
Linked list data structures
Variable size transmit/receive FIFO
Per-channel message length check
Select no length checking
Select from two 12-bit registers to
compare message length
Maximum length 16,384 Bytes
Direct PCI bus interface
32-bit, 66 or 33 MHz operation
Bus master and slave operation
PCI Version 2.1
Local Expansion Bus interface (EBUS)
32-bit multiplexed address/data bus
Burst access up to 64 Bytes
Low power, 3.3/2.5 V CMOS operation
JTAG boundary scan access port
208-pin PQFP/surface-mount package
BGA
Available in Green (ROHS compliant) as
well as standard version
Multichannel Synchronous
Communications Controller (MUSYCC™)
Product Description
The CN8478, CN8474A, CN8472A, and CN8471A are advanced Multichannel
Synchronous Communication Controllers (MUSYCCs) that format and deformat
up to 256 (CN8478), 128 (CN8474A), 64 (CN8472A), or 32 (CN8471A) HDLC
channels in a single CMOS integrated circuit. MUSYCC operates at Layer 2 of
the Open Systems Interconnection (OSI) protocol reference model. MUSYCC
provides a comprehensive, high-density solution for processing HDLC channels
for internetworking applications such as Frame Relay, ISDN D-channel signaling,
X.25, Signaling System 7 (SS7), DXI, ISUP, and LAN/WAN data transport. Under
minimal host supervision, MUSYCC manages a linked list of channel data
buffers in host memory by performing Direct Memory Access (DMA) of the
HDLC channels.
MUSYCC interfaces with eight independent serial data streams, such as T1/E1
signals, and then transfers data across the popular 32-bit Peripheral Component
Interface (PCI) bus to system memory at a rate of up to 66 MHz. Each serial
interface can be operated at up to 8.192 MHz. Logical channels can be mapped
as any combination of DS0 time slots to support ISDN hyperchannels (Nx64
kbps) or as any number of bits in a DS0 for subchanneling applications (Nx8
kbps). MUSYCC also includes a 32-bit expansion port for bridging the PCI bus to
local microprocessors or peripherals. A JTAG port enables boundary-scan
testing to replace bed-of-nails board testing.
Device drivers for Linux, VxWorks
®
operating systems are available under a no-
fee license agreement from Mindspeed. The device drivers include C source
code and supporting software documents.
Functional Block Diagram
Host
Interface
Channel Group 0 – Serial Interface
DMA
Controller
Tx/Rx-DMAC
Interrupt
Controller
Bit-Level
Processor
Tx/Rx-BLP
Port
Interface
Tx/Rx
Device
Configuration
Registers
Channel Group 1 – Serial Interface
Channel Group 2 – Serial Interface
Channel Group 3 – Serial Interface
Channel Group 4 – Serial Interface
Channel Group 5 – Serial Interface
Channel Group 6 – Serial Interface
Channel Group 7 – Serial Interface
Note: Number of serial interfaces is device-dependent.
Serial Data Bus
PCI Bus
PCI
Interface
Applications
ISDN basic-rate or primary-rate interfaces
ISDN D-channel controller
Routers
Cellular base station switch controller
CSU/DSU
Protocol converter
Packet data switch
Frame relay switches/Frame Relay Access
Devices (FRAD)
DXI network interface
Distributed packet-based communications
system
Access multiplexer/concentrator
PCI
Configuration
Space
(Function 0)
PCI
Configuration
Space
(Function 1)
Expanion Bus Interface
28478-DSH-002-D
Mindspeed Technologies
®
Preliminary Information / Mindspeed Proprietary and Confidential
Local Bus
Boundary Scan and Test Access
iii
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0
2.0
System Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1.1
PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1.2
PCI Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1.3
PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Function 0 Network Controller—PCI Master and Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Function 1 Expansion Bus Bridge, PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
PCI Bus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
PCI Throughput and Latency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.2.6.1
PCI Bus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
2.2.6.2
2.2.6.3
Latency Computation—Single Dword Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Latency Computation—Burst Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
2.2
3.0
Expansion Bus (EBUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Address Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Data Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Bus Access Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
PCI to EBUS Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
28478-DSH-002-D
Mindspeed Technologies
®
Preliminary Information / Mindspeed Proprietary and Confidential
iv
Table of Contents
3.1.10
3.1.11
Arbitration52
Connection53
4.0
Serial Interface56
4.1
4.2
4.3
4.4
4.5
Serial Port Interface56
Bit Level Processor57
DMA Controller57
Interrupt Controller57
Channelized Port Mode57
4.5.1
Hyperchannels (Nx64)58
4.5.2
Subchannels (Nx8)58
4.5.3
Frame Synchronization Flywheel59
4.5.4
Change-of-Frame Alignment63
4.5.5
Out-of-Frame63
Serial Port Mapping64
Tx and Rx FIFO Buffer Allocation and Management65
4.7.1
4.7.2
4.7.3
Example Channel BUFFLOC and BUFFLEN Specification67
Receiving Bit Stream68
Transmitting Bit Stream68
4.7.3.1
Transmit Data Bit Output Value Determination69
4.6
4.7
5.0
Memory Organization70
5.1
Memory Architecture70
5.1.1
Register Map Access and Shared Memory Access71
5.1.2
Memory Access Illustration74
Descriptors76
5.2.1
Host Interface Level Descriptors77
5.2.1.1
Global Configuration Descriptor77
5.2.1.2
5.2.2
Dual Address Cycle Base Pointer79
Channel Group Level Descriptors80
5.2.2.1
Group Base Pointer80
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.2.7
5.2.2.8
5.2.3
Service Request80
Group Configuration Descriptor83
Memory Protection Descriptor85
Port Configuration Descriptor85
Message Length Descriptor86
Time Slot Map87
Subchannel Map89
5.2
Channel Level Descriptors91
28478-DSH-002-D
Mindspeed Technologies
®
Preliminary Information / Mindspeed Proprietary and Confidential
v
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