HV300
___________________________________________________________________________________________
Engineering Specification
HV300 Negative Supply Hot Swap Controller
(Active High PWRGD)
Ordering Information
V
EE
Min
-90V
Max
-10V
8 Pin
Plastic DIP
HV300P
Package Options
8 Pin
SOIC
HV300LG
Dice
HV300X
Features
•
•
•
•
•
•
•
•
•
•
•
-10V to -90V Input Voltage Range
0.55mA Typical Operating Supply Current
0.33mA Standby Mode Operating Supply Current
Programmable Input Under Voltage Limit with Hysteresis
Programmable Input Over Voltage Limit with Hysteresis
Programmable Current Limit
Programmable Start Delay, Ramp to Current Limit and PWRGD
PWRGD Status Output for Controlling Loads
Well Defined Gate Regulation Over Input Voltage Range
True Current Loop Control
Few External Components
General Description
The Supertex HV300, an 8-pin negative supply Hot Swap Controller
for live backplane systems, is designed to facilitate the safe insertion
or removal of circuit cards.
After an initial delay, the inrush current is limited by means of
controlling the gate of an external N-channel MOSFET that will ramp
up the current to a maximum value programmed by an external
resistor. The current ramp rate and initial time delay are
programmable by means of an external capacitor connected to the
RAMP pin. When the load capacitor reaches full charge and the
controller emerges from current limit mode an additional time delay
occurs. Thereafter the external N-channel MOSFET is switched to
full on, the open drain PWRGD output pull down is released and the
controller transitions to a low power standby mode.
Other features include programmable over voltage and under voltage
detection of the input voltage and an internal voltage regulator to
create a well-regulated gate drive voltage. The unique control loop
scheme provides full current control and limiting during start up.
Applications
•
•
•
•
•
•
•
•
•
Central Office Switching
POTS Line Cards
ISDN Line Cards
xDSL Line Cards
PBX Systems
Powered Ethernet for VoIP
Distributed Power Systems
Negative Power Supply Control
Antenna and Fixed Wireless Systems
Absolute Maximum Ratings
V
EE
reference to V
DD
pin
V
PWRGD
referenced to V
EE
Voltage
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
+0.5V to -100V
-0.5V to +100V
-40°C to +85°C
-40°C to +125°C
-65°C to +150°C
Functional Block Diagram
VDD
Internal
Supply
Regulator
UVLO
and
POR
Band Gap
Reference
Vref
Vdd
UV
PWRGD
Vref
LOGIC
OV
Vdd
Vref
Switch
Vref
VEE
SENSE
RAMP
GATE
Prepared by the Telecom Group
1 of 5
Rev. E
7/19/2001
_________________________________________________________________ ______________________________________________
Supertex, Inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV300
___________________________________________________________________________________________
Electrical Characteristics
(-40°C
!
T
A
!
+85°C unless otherwise noted)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Supply
(Referenced to V
DD
pin)
V
EE
I
EE
I
EE
Supply Voltage
Supply Current
Standby Mode Supply Current
-90
550
330
-10
650
400
V
µA
µA
V
EE
= -48V, Mode = Limiting
V
EE
= -48V, Mode = Standby
OV and UV Control
(Referenced to V
EE
pin)
V
UVH
V
UVL
V
UVH
I
UV
V
OVH
V
OVL
V
OVH
I
OV
UV High Threshold
UV Low Threshold
UV Hysteresis
UV Input Current
OV High Threshold
OV Low Threshold
OV Hysteresis
OV Input Current
1.26
1.16
100
1
1.26
1.16
100
1
V
V
mV
nA
V
V
mV
nA
V
OV
= V
EE
+ 0.5V
V
UV
= V
EE
+ 1.9V
Low to High Transition
High to Low Transition
Low to High Transition
High to Low Transition
Current Limit
(Referenced to V
EE
pin)
V
SENSE
R
SENSE
Current Limit Threshold Voltage
Sense Resistor Value (SENSE to V
EE
)
40
50
50
60
mV
mΩ
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V
For 1A Current Limit
Gate Drive Output
(Referenced to V
EE
pin)
V
GATE
I
GATEUP
I
GATEDOWN
Maximum Gate Drive Voltage
Gate Drive Pull-Up Current
Gate Drive Pull-Down Current
9
500
40
10
11
V
µA
mA
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V
V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V,
V
GATE
= V
EE
V
UV
= V
EE
, V
OV
= V
EE
+ 0.5V, V
GATE
=
V
EE
+ 4V
Timing Control -
Test Conditions: C
LOAD
=100µF, C
RAMP
=10nF, V
UV
= V
EE
+ 1.9V, V
OV
= V
EE
+ 0.5V, External MOSFET is IRF530*
I
RAMP
t
POR
t
RISE
t
LIMIT
t
PWRGD
V
RAMP
Ramp Pin Output Current
Time from UV to Gate Turn On
Time from Gate Turn On to V
SENSE
Limit
Duration of Current Limit Mode
Time from Current Limit to PWRGD
Voltage on Ramp Pin in Current Limit Mode
2
400
<5
5
3.6
10
µA
ms
µs
ms
ms
V
(Note 2)
(Note 1)
Power Good Output
(Referenced to V
EE
pin)
V
PWRGD
V
PWRGD
Power Good Pin Breakdown Voltage
Power Good Pin Output Low Voltage
90
0.5
0.8
V
V
I
PWRGD
= 1mA
Dynamic Characteristics
t
GATEHLOV
t
GATEHLUV
Note 1:
OV Comparator Transition
UV Comparator Transition
<500
<500
ns
ns
This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this
timing.
This voltage depends on the characteristics of the external N-Channel MOSFET.
V
to
= 3V for an IRF530.
Note 2:
*IRF530 is a registered trademark of International Rectifier.
Prepared by the Telecom Group
2 of 5
Rev. E
7/19/2001
_________________________________________________________________ ______________________________________________
Supertex, Inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV300
_______________________________________________________________________________________
Pinout
PWRGD
1
8
VDD
OV
2
HV300
7
RAMP
UV
3
6
GATE
VEE
4
5
SENSE
Pin Description
PWRGD –
The Power Good Output Pin is held Low on initial power
application and will release its high voltage (V
EE
+ 90V) open drain
when the external MOSFET is fully turned on. This pin may be
used as an enable control when connected directly to a PWM
power module.
OV –
This Over Voltage sense pin, when raised above its high
threshold will immediately cause the GATE pin to be pulled low.
The GATE pin will remain low until the voltage on this pin falls
below the low threshold limit and a new start-up cycle will engage.
UV
– This Under Voltage sense pin, when below its low threshold
limit will ensure that the GATE pin is low. The GATE pin will remain
low until the voltage on this pin rises above the high threshold and a
new start-up cycle wil engage.
V
EE
– This pin is the negative voltage power supply input to the
circuit.
V
DD
–
This pin is the positive voltage power supply input to the
circuit.
RAMP –
This pin provides a current output so that a timing ramp
voltage is generated when a capacitor is connected. The initial
portion of the ramp provides a time delay, which in conjunction with
the Under Voltage detection circuit eliminates circuit card insertion
contact bounce. The RAMP pin also controls the delay between the
current limit mode disengaging and the PWRGD high voltage open
drain pull down releasing; as well as the current rise profile after the
initial turn on delay.
GATE –
This is the Gate Driver Output for the external N-Channel
MOSFET.
SENSE –
The current sense resistor connected from this pin to
V
EE
Pin programs the current limit. Constant current output mode is
established when the voltage drop across this resistor reaches
50mV.
Package Dimensions
Prepared by the Telecom Group
3 of 5
Rev. E
7/19/2001
_________________________________________________________________ ______________________________________________
Supertex, Inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV300
___________________________________________________________________________________________________
Functional Description
Insertion into Hot Backplanes
Telecom, Data Network and some Computer applications require the
ability to insert and remove circuit cards from systems without
powering down the entire system. All circuit cards have some filter
capacitance on the power rails, which is especially true in circuit cards
or network terminal equipment utilizing distributed power systems.
The insertion can result in high inrush currents that can cause
damage to connector and circuit cards and may result in
unacceptable disturbances on the system backplane power rails.
The HV300 was designed to allow the insertion of these circuit cards
or connection of terminal equipment by eliminating these inrush
currents and powering up these circuits in a controlled manner after
full connector insertion has been achieved. The HV300 is intended
Description of operation
On initial power application an internal regulator seeks to provide 10
Volts for the internal IC circuitry. Until the proper internal voltage is
achieved all circuits are held reset, the open drain PWRGD output is
pulled low to inhibit the start of any load circuitry and the gate to
source voltage of the external N-channel MOSFET is held low. Once
the internal under voltage lock out (UVLO) has been satisfied, the
circuit checks the input supply voltage under voltage (UV) and over
voltage (OV) sense circuits to ensure that the input voltage is within
acceptable programmed limits. These limits are determined by the
selected values of resistors R1, R2 and R3, which form a voltage
divider.
Assuming the above conditions are satisfied and while continuing to
hold the PWRGD output low and the external MOSFET GATE
voltage low, the current source feeding the RAMP pin is turned on.
The external capacitor connected to it begins to charge, thus starting
an initial time delay determined by the value of the capacitor. If an
interruption of the input power occurs during this time (i.e. caused by
contact bounce) or the OV or UV limits are exceeded, an immediate
reset occurs and the external capacitor connected to the RAMP pin
is discharged.
When the voltage on the RAMP pin reaches an internally set voltage
limit, the gate drive circuitry begins to turn on the external MOSFET;
allowing the current to softly rise over a period of a few hundred
micro-seconds to the current limit set point. While the circuit is
limiting current, the voltage on the RAMP pin will be fixed.
Depending on the value of the load capacitance and the
programmed current limit, charging may continue for some time.
The magnitude of the current limit is programmed by comparing a
voltage developed by a sense resistor connected between the V
EE
and SENSE pins to 50mV (Typical). Once the load capacitor has
been charged, the current will drop which will cause the ramp voltage
to continue rising; providing yet another programmed delay.
When the ramp voltage is within 1.2V of the internally regulated
voltage, the controller will force the GATE full on and will release the
pull down on the PWRGD pin and the circuit will transition to a low
power standby mode. The PWRGD pin is often used as an enable
for downstream DC/DC converter loads.
At any time during the start up cycle or thereafter, crossing the UV
and OV limits (including hysteresis) will cause an immediate reset of
all internal circuitry. Thereafter the start up process will begin again.
V
DD
UV
V
SENSE
V
RAMP
V
GATE
V
PWRGD
V
DD1
V
DRAIN
I
LIMIT
to provide this function on a negative supply rail in the range of -10 to
-90 Volts.
Note: V
DD1
is an internal node in the IC
Waveforms
Prepared by the Telecom Group
4 of 5
Rev. E
7/19/2001
_________________________________________________________________ ______________________________________________
Supertex, Inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV300
___________________________________________________________________________________________
Typical Application Circuit
GND
Long
Pin
8
Short
Pin
487K
Jumper
VDD
PWRGD
R1
3
9.09K
R2
2
9.09K
R3
OV
ENABLE
UV
+5V
DC/DC
PWM
CONVERTER
COM
1
GND
HV300
Cload
RAMP
7
VEE
4
SENSE
5
GATE
6
NOTES: 1. Undervoltage Lockout (UV) set to 35V.
2. Overvoltage Lockout (OV) set to 65V.
3. Remove Jumper if Short Pin is used.
10nF
Long
Pin
C1
-48V
R4
0.05
Q1
IRF530
Application Information
Under Voltage and Over Voltage Detection
The UV and OV pins are connected to comparators with nominal
1.21V thresholds and 100mV of hysteresis (1.21V
±
50mV). They
are used to detect under voltage and over voltage conditions at the
input to the circuit. Whenever the OV pin rises above its threshold
or the UV pin falls below its threshold the GATE voltage is
immediately pulled low, the PWRGD pin is pulled low and the
external capacitor connected to the RAMP pin is discharged.
The under voltage and over voltage trip points can be programmed
by means of the three resistor divider formed by R1, R2 and R3.
Since the input currents on the UV and OV pins are negligible the
resistor values may be calculated as follows:
UV = V
UVH
= 1.26 =
V
EEUV
* (R2+R3) / (R1+R2+R3)
OV = V
OVL
= 1.16 =
V
EEOV
* R3 / (R1+R2+R3)
Where
V
EEUV
and
V
EEOV
are Under & Over Voltage Set points.
If we select a divider current of 100µA at a nominal operating input
voltage of 50 Volts then
(R1+R2+R3) = 50V / 100µA = 500K Ohms
From the second equation for an Over voltage set point of 65 Volts
the value of R3 may be calculated.
OV = 1.16 = 65 * R3 / 500K
R3 = (1.16 * 500K) / 65; Let R3 = 9K
From the first equation for an Under Voltage set point of 35 Volts the
value R2 can be calculated.
UV = 1.26 = 35 * (R2 + R3) / 500K
R2 = (1.26 * 500K) / 35 – 9K
R2 = 9K
Then R1 = 500K – (R2 +R3); R1 = 482K
Current Limit
The current limit magnitude above which the current will not be
allowed to rise during startup is programmed using a sense resistor
connected from the SENSE pin to V
EE
pin. For example to
program a current limit of 1A, one would choose a resistor as
follows:
Rsense = 50mV / Isense
Rsense = 50mV / 1A
Rsense = 50mΩ
Prepared by the Telecom Group
5 of 5
Rev. E
7/19/2001
_________________________________________________________________ ______________________________________________
Supertex, Inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
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