DATA SHEET
µ
PD703014A, 703014AY, 703015A,
703015AY, 703017A, 703017AY
V850/SA1
32-/16-BIT SINGLE-CHIP MICROCONTROLLER
TM
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-
chip microcontrollers that include the CPU core of the V850 Family
TM
, and peripheral functions such as ROM/RAM,
timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,
all of which are instructions suited to digital servo control applications. As a real-time control system, this device
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SA1 User’s Manual Hardware:
U12768E
TM
U10243E
V850 Family User’s Manual Architecture:
FEATURES
{
Number of instructions: 74
{
Minimum instruction execution time:
59 ns (@ 17 MHz operation with main system clock (f
XX
))
50 ns (@ 20 MHz operation with main system clock (f
XX
))
30.5
µ
s (@ 32.768 kHz operation with subsystem clock (f
XT
))
{
General-purpose registers: 32 bits
×
32 registers
{
Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
{
Memory space:
16 MB linear address space
Memory block allocation function: 2 MB per block
{
External bus interface: 16-bit data bus
Address bus: Separate output enabled
{
Internal memory
Mask ROM: 64 KB (
µ
PD703014A, 703014AY)
128 KB (
µ
PD703015A, 703015AY)
256 KB (
µ
PD703017A, 703017AY)
RAM: 4 KB
(
µ
PD703014A, 703014AY, 703015A, 703015AY)
8 KB (
µ
PD703017A, 703017AY)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
{
Interrupts and exception
External: 8, internal: 23, exception: 1
{
I/O lines Total: 85
{
Timer/counters
16-bit timer:
8-bit timer:
2 channels
4 channels
{
Watch timer: 1 channel
{
Watchdog timer: 1 channel
{
Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I
2
C bus interface
(
µ
PD703014AY, 703015AY, 703017AY)
{
A/D converter: 12 channels
{
DMA controller: 3 channels
{
RTP: 8 bits
×
1 channel or 4 bits
×
2 channels
{
Power-saving functions: HALT/IDLE/STOP modes
{
Packages: 100-pin plastic LQFP (14
×
14)
121-pin plastic FBGA (12
×
12)
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14526EJ2V0DS00 (2nd edition)
Date Published September 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
µ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
APPLICATIONS
{
Low-power portable devices
Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number
Package
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
100-pin plastic LQFP (fine-pitch) (14
×
14)
121-pin plastic FBGA (12
×
12)
Internal ROM
64 KB (Mask ROM)
64 KB (Mask ROM)
64 KB (Mask ROM)
64 KB (Mask ROM)
128 KB (Mask ROM)
128 KB (Mask ROM)
128 KB (Mask ROM)
128 KB (Mask ROM)
256 KB (Mask ROM)
256 KB (Mask ROM)
256 KB (Mask ROM)
256 KB (Mask ROM)
µ
PD703014AGC-×××-8EU
µ
PD703014AF1-×××-EA6
µ
PD703014AYGC-×××-8EU
µ
PD703014AYF1-×××-EA6
µ
PD703015AGC-×××-8EU
µ
PD703015AF1-×××-EA6
µ
PD703015AYGC-×××-8EU
µ
PD703015AYF1-×××-EA6
µ
PD703017AGC-×××-8EU
µ
PD703017AF1-×××-EA6
µ
PD703017AYGC-×××-8EU
µ
PD703017AYF1-×××-EA6
Remark
×××
indicates ROM code suffix.
2
Data Sheet U14526EJ2V0DS00
µ
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
PIN IDENTIFICATION
A1 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI11:
ASCK0, ASCK1:
ASTB:
AV
DD
:
AV
REF
:
AV
SS
:
BV
DD
:
BV
SS
:
CLKOUT:
DSTB:
HLDAK:
HLDRQ:
IC:
INTP0 to INTP6:
LBEN:
NMI:
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
P70 to P77:
P80 to P83:
Address Bus
Address/Data Bus
AD Trigger Input
Analog Input
Asynchronous Serial Clock
Address Strobe
Analog V
DD
Analog Reference Voltage
Analog V
SS
Power Supply for Bus Interface
Ground for Bus Interface
Clock Output
Data Strobe
Hold Acknowledge
Hold Request
Internally Connected
Interrupt Request From Peripherals
Lower Byte Enable
Non-maskable Interrupt Request
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
P90 to P96:
P100 to P107:
P110 to P114:
P120:
RD:
RESET:
RTP0 to RTP7:
RTPTRG:
R/W:
RXD0, RXD1:
SCK0 to SCK2:
SCL
Note
Port 9
Port 10
Port 11
Port 12
Read
Reset
Real-time Port
RTP Trigger
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Input
Timer Output
Transmit Data
Upper Byte Enable
Power Supply
Ground
Wait
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main Clock
Crystal for Sub-clock
:
:
SDA
Note
SI0 to SI2:
SO0 to SO2:
TI00, TI01, TI10, :
TI11, TI2 to TI5
TO0 to TO5:
TXD0, TXD1:
UBEN:
V
DD
:
V
SS
:
WAIT:
WRH:
WRL:
X1, X2:
XT1, XT2:
Note
Applies to the
µ
PD703014AY, 703015AY, and 703017AY only.
Data Sheet U14526EJ2V0DS00
5
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