DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD70741
V821
TM
32-/16-BIT MICROPROCESSOR
The
µ
PD70741 (V821) is a 32/16-bit RISC microprocessor that uses, as its processor core, the high-
performance 32-bit microprocessor
µ
PD70732 (V810
TM
) designed for built-in control applications. It incorporates
peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial
interface, and interrupt controller.
The V821, which offers quick real-time response, high-speed integer instructions, bit string instructions, and
floating-point instructions, is ideally suited to use in OA equipment such as printers and facsimiles, image
processing devices such as those used in navigation units, portable devices, and other devices demanding
excellent cost performance.
The functions are described in detail in the following User’s Manuals, which should be read before
starting design work.
• V821 User’s Manual Hardware
: U10077E
• V810 Family
TM
User’s Manual Architecture : U10082E
FEATURES
The V810 32-bit microprocessor is used as the CPU core
• Separate address/data bus
Address bus : 24 bits
Data bus
: 16 bits
• Built-in 1-Kbyte instruction cache memory
• Pipeline structure of 1-clock pitch
• Internal 4-Gbyte linear address space
• 32-bit general-purpose registers: 32
Instructions ideal for various application fields
• Floating-point operation instructions and bit string
instructions
Interrupts controller
• Nonmaskable : 1 external input
• Maskable
: 8 external inputs and 11 types of
internal sources
• Priorities can be specified in units of four groups.
Wait control unit
• Capable of CS control over four blocks in both memory
and I/O spaces.
• Linear address space of each block: 16M bytes
Memory access control functions
• Supports DRAM high-speed page mode.
• Supports page-ROM page mode.
DMA controller (DMAC): 2 channels
• Maximum transfer count: 65 536
• Two transfer types (fly-by (1-cycle) transfer and
2-cycle transfer)
• Three transfer modes (single transfer, single-
step transfer, and block transfer)
Serial interfaces : 2 channels
• Asynchronous serial interface (UART):
1 channel
• Synchronous serial interface (CSI):
1 channel
Real-time pulse unit
• 16-bit timer/event counter : 1 channel
• 16-bit interval timer
Watchdog timer functions
Clock generator functions
Standby functions (HALT, IDLE, and STOP modes)
: 1 channel
The information in this document is subject to change without notice.
Document No. U11678EJ4V0DS00 (4th edition)
Date Published June 1998 J CP(K)
Printed in Japan
The mark
shows major revised points.
©
1996
µ
PD70741
ORDERING INFORMATION
Part number
Package
100-pin plastic LQFP (fine pitch) (14
×
14
×
1.40 mm)
µ
PD70741GC-25-8EU
PIN CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch) (14
×
14 mm)
µ
PD70741GC-25-8EU
Caution Connect the IC pin to GND through a resistor.
2
GND
IORD
IOWR
NMI
HLDRQ
HLDAK
RXD/P09/TC
TXD/P08/UBE
SCLK/P07
SO/P06
SI/P05
DACK1/P04
DREQ1/P03
DACK0/P02
DREQ0/P01
GND
V
DD
TCLR/P00
BLOCK/WDTOUT
INTP03
INTP02/TO01
INTP01
INTP00/TO00
INTP13/TI
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
DD
RAS
UMWR
LMWR/WE
MRD
READY
CS0/REFRQ
CS1
CS2
CS3
A12
A13
A14
A15
A16
GND
V
DD
A17
A18
A19
A20
A21
A22
A23
V
DD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
LCAS
UCAS
GND
X1
X2
V
DD
CLKOUT
V
DD
GND
A11
A10
A9
A8
A7
A6
GND
V
DD
A5
A4
A3
A2
A1
A0
V
DD
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
D15
D14
D13
D12
D11
D10
D9
D8
GND
V
DD
D7
D6
D5
D4
D3
D2
D1
D0
IC
RESET
INTP10
INTP11
INTP12
GND
µ
PD70741
PIN NAMES
A0-A23
BLOCK
CLKOUT
CS0-CS3
D0-D15
DACK0, DACK1
DREQ0, DREQ1
HLDAK
HLDRQ
INTP00-INTP03, INTP10-INTP13
IORD
IOWR
LCAS
LMWR
MRD
NMI
P00-P09
RAS
READY
REFRQ
RESET
RXD
SCLK
SI
SO
TC
TCLR
TI
TO00, TO01
TXD
UBE
UCAS
UMWR
WDTOUT
WE
X1, X2
: Address Bus
: Bus Lock
: System Clock Out
: Chip Select
: Data Bus
: DMA Acknowledge
: DMA Request
: Hold Acknowledge
: Hold Request
: Interrupt Request
: I/O Read
: I/O Write
: Lower Column Address Strobe
: Lower Memory Write
: Memory Read
: Non-maskable Interrupt Request
: Port
: Row Address Strobe
: Ready
: Refresh Request
: Reset
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
: Terminal Count
: Timer Clear
: Timer Input
: Timer Output
: Transmit Data
: Upper Byte Enable
: Upper Column Address Strobe
: Upper Memory Write
: Watchdog Timer Output
: Write Enable
: Crystal Oscillator
3
µ
PD70741
INTERNAL BLOCK DIAGRAM
CLKOUT
TI
V821
X1
X2
RESET
CG
CPU
(V810)
ICU
RPU
4
TO00,TO01
TCLR
INTP00-INTP03,
INTP10-INTP13
TXD
RXD
SCLK
SI
SO
PORT00-PORT09
UART
WDTOUT
WDT
CSI
HLDAK
HLDRQ
DREQ0, DREQ1
DACK0, DACK1
TC
BAU
PORT
DMAC
DRAMC
BIU
ROMC
WCU/CS
NMI
A0-A23
D0-D15
UBE
RAS
LCAS
UCAS
REFRQ
WE
MRD
IORD
IOWR
LMWR
UMWR
READY
CS0-CS3
4
µ
PD70741
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1
1.2
1.3
Port Pins .........................................................................................................................................
Non-Port Pins .................................................................................................................................
Pin I/O Circuits and Processing of Unused Pins ......................................................................
8
8
8
10
2.
INTERNAL UNITS ......................................................................................................................
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Bus Interface Unit (BIU) ................................................................................................................
Wait Control Unit (WCU) ...............................................................................................................
DRAM Controller (DRAMC) ...........................................................................................................
ROM Controller (ROMC) ................................................................................................................
Interrupt Controller ........................................................................................................................
DMA Controller (DMAC) ................................................................................................................
Serial Interfaces (UART/CSI) ........................................................................................................
Real-Time Pulse Unit (RPU) .........................................................................................................
Watchdog Timer (WDT) .................................................................................................................
Clock Generator (CG) ....................................................................................................................
Bus Arbitration Unit (BAU) ...........................................................................................................
Port ..................................................................................................................................................
12
12
12
12
12
12
12
12
12
13
13
13
13
3.
CPU FUNCTIONS .......................................................................................................................
3.1
3.2
Features ..........................................................................................................................................
Address Space ...............................................................................................................................
3.2.1
3.2.2
3.3
3.3.1
3.3.2
3.4
3.5
Memory map ...................................................................................................................
I/O map ............................................................................................................................
Program register set .....................................................................................................
System register set ........................................................................................................
14
14
14
15
16
17
18
19
20
23
23
25
26
CPU Register Set ...........................................................................................................................
Built-in Peripheral I/O Registers ..................................................................................................
Data Types ......................................................................................................................................
3.5.1
3.5.2
Data types .......................................................................................................................
Data alignment ...............................................................................................................
3.6
Cache ...............................................................................................................................................
4.
INTERRUPT/EXCEPTION HANDLING FUNCTIONS ...............................................................
4.1
Features ..........................................................................................................................................
27
27
5.
WAIT CONTROL FUNCTIONS ..................................................................................................
5.1
Features ..........................................................................................................................................
30
30
5
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