DATA SHEET
MOS INTEGRATED CIRCUITS
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY
V850/SB2
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
TM
The
µ
PD703037A, 703037AY, 70F3037A, and 70F3037AY (V850/SB2) are 32-/16-bit single-chip microcontrollers
of the V850 Family
TM
for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter,
DMA controller, and so on are integrated on a single chip.
The
µ
PD70F3037A and 70F3037AY have flash memory in place of the internal mask ROM of the
µ
PD703037A
and 703037AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
The
µ
PD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY with different ROM/RAM
capacity are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
TM
V850/SB1 , V850/SB2 User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{
Number of instructions: 74
{
Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
{
General-purpose registers: 32 bits
×
32 registers
{
Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{
Memory space: 16 MB linear address space
{
Internal memory ROM: 512 KB (
µ
PD703037A, 703037AY: mask ROM)
512 KB (
µ
PD70F3037A, 70F3037AY: flash memory)
RAM: 24 KB (
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY)
{
Interrupt/exception:
µ
PD703037A, 70F3037A, (external: 8, internal: 33 sources, exception: 1 source)
µ
PD703037AY, 70F3037AY (external: 8, internal: 34 sources, exception: 1 source)
{
I/O lines Total: 83
{
Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{
Watch timer: 1 channel
{
Watchdog timer: 1 channel
{
IEBus controller: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14894EJ1V0DS00 (1st edition)
Date Published August 2000 J CP(K)
Printed in Japan
©
2000
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY
{
Serial interface
•
Asynchronous serial interface (UART0, UART1)
•
Clocked serial interface (CSI0 to CSI3)
•
3-wire variable length serial interface (CSI4)
2
2
2
•
I C bus interface (I C0, I C1) (
µ
PD703037AY, 70F3037AY only)
{
10-bit resolution A/D converter: 12 channels
{
DMA controller: 6 channels
{
Real-time output port: 8 bits
×
1 channel or 4 bits
×
2 channels
{
ROM correction: 4 places can be corrected
{
Power-saving function: HALT/IDLE/STOP modes
{
Packages: 100-pin plastic QFP (14
×
20)
{
µ
PD70F3037A, 70F3037AY
•
Can be replaced with
µ
PD703037A and 703037AY (internal mask ROM) in mass production
APPLICATIONS
{
AV equipment (audio, car audio, VCR, TV, etc.)
ORDERING INFORMATION
Part Number
Package
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
Internal ROM
Mask ROM (512 KB)
Mask ROM (512 KB)
Flash memory (512 KB)
Flash memory (512 KB)
µ
PD703037AGF-×××
×××-3BA
×××
µ
PD703037AYGF-×××
×××-3BA
×××
Note
µ
PD70F3037AGF-3BA
µ
PD70F3037AYGF-3BA
Note
Note
Under development
Remarks 1.
×××
indicates ROM code suffix.
2.
ROMless versions are not provided.
2
Data Sheet U14894EJ1V0DS00
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
TI00, TI01,
TI10, TI11
TO0, TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0
Note 3
SCK0/SCL0
Note 3
SO2
SI2/SDA1
Note 3
SCK2/SCL1
Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
KR0 to KR7
ROM
INTC
Note 1
CPU
PC
32-bit barrel
shifter
ROM
correction
Multiplier
16
×
16
→
32
BCU
ALU
Instruction
queue
HLDRQ (P96)
HLDAK (P95)
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT (P110)
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
Timer/counters
16-bit timer
: TM0, TM1
8-bit timer
: TM2 to TM7
SIO
CSI0/I
2
C0
Note 3
CSI2/I
2
C1
Note 3
RAM
System
registers
General registers
32 bits
×
32
Note 2
CSI1/UART0
Ports
CSI3/UART1
Variable length
CSI4
Key return
function
DMAC: 6ch
Watch timer
Watchdog timer
V
SS
BV
DD
BV
SS
EV
DD
EV
SS
V
PP
Note 4
IC
Note 5
RTP
A/D
converter
CG
CLKOUT
X1
X2
XT1
XT2
RESET
P110 to P113
P100 to P107
P90 to P96
P80 to P83
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
RTP0 to RTP7
RTPTRG
AV
DD
AV
REF
AV
SS
ANI0 to ANI11
ADTRG
3.0 V
Regulator
V
DD
IETX
IERX
IEBus
Notes 1.
2.
3.
4.
5.
µ
PD703037A, 703037AY:
512 KB (mask ROM)
µ
PD70F3037A, 70F3037AY: 512 KB (flash memory)
µ
PD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB
I
2
C bus interface and SDAn and SCLn pins (n = 0, 1) are available only in the
µ
PD703037AY and
70F3037AY.
µ
PD70F3037A, 70F3037AY
µ
PD703037A, 703037AY
REGC
Data Sheet U14894EJ1V0DS00
5
FPGA/CPLD
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