IDT74ALVCH162832
3.3V CMOS 1-BIT TO 2-BIT ADDRESS REGISTER/DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 1-BIT TO 4-BIT
ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS AND
BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.50mm pitch TSSOP package
– Extended commercial range of – 40°C to +85°C
– V
CC
= 3.3V ±0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ±0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH162832:
– Balanced Output Drivers: ±12mA
– Low switching noise
–
–
–
IDT74ALVCH162832
DESCRIPTION:
This 1-bit to 4-bit address register/driver is built using advanced dual
metal CMOS technology. This device is ideal for use in applications in
which a single address bus is driving four separate memory locations.
The ALVCH162832 can be used as a buffer or a register, depending on
the logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer mode. The outputs
follow the inputs and are controlled by the two output-enable (OE)
controls. Each OE controls two groups of seven outputs. When SEL is
logic low, the device is in the register mode. The register is an edge-
triggered D-type flip-flop. On the positive transition of the clock (CLK)
input, data at the A inputs is stored in the internal registers. OE controls
operate the same as in buffer mode.
The ALVCH162832 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCH162832 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
•
•
•
•
Memory subsystems
PC motherboards and servers
Workstations
Telecommunication applications
FUNCTIONAL BLOCK DIAGRAM
OE
1
16
5
OE
2
17
1
Y
1
CLK
15
4
CLK
2
2
Y
1
A
1
7
3
Y
1
D
Q
1
4
Y
1
SEL
18
TO 6 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4549/-
IDT74ALVCH162832
3.3V CMOS 1-BIT TO 2-BIT ADDRESS REGISTER/DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
4
Y
1
3
Y
1
ABSOLUTE MAXIMUM RATING
1
Y
2
2
Y
2
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SO64-1 50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
2
Y
1
1
Y
1
GND
3
Y
2
4
Y
2
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
V
CC
A
1
GND
A
2
GND
A
3
V
CC
NC
GND
CLK
OE
1
OE
2
SEL
GND
A
4
A
5
V
CC
GND
A
6
GND
A
7
V
CC
4
Y
7
3
Y
7
V
CC
1
Y
3
2
Y
3
GND
3
Y
3
4
Y
3
GND
V
CC
GND
1
Y
4
2
Y
4
3
Y
4
4
Y
4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
GND
1
Y
5
2
Y
5
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
V
CC
3
Y
5
4
Y
5
GND
GND
V
CC
1
Y
6
2
Y
6
NOTE:
1. As applicable to the device type.
GND
2
Y
7
1
Y
7
GND
3
Y
6
4
Y
6
FUNCTION TABLE
Inputs
OEx
H
L
L
L
L
SEL
X
H
H
L
L
CLK
X
X
X
↑
↑
(1)
Output
Ax
X
L
H
L
H
xYx
Z
L
H
L
H
TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OEx
CLK
SEL
Ax
xYx
NC
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Select Input
Data Inputs
(1)
3-State Outputs
No Internal Connection
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ =
LOW-to-HIGH Transition
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
2
IDT74ALVCH162832
3.3V CMOS 1-BIT TO 2-BIT ADDRESS REGISTER/DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH162832
3.3V CMOS 1-BIT TO 2-BIT ADDRESS REGISTER/DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
V
CC
= 2.7V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
NEW16link
Unit
V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
119
22
V
CC
= 3.3V ± 0.3V
Typical
132
25
Unit
pF
pF
SWITCHING CHARACTERISTICS
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
SU
t
H
t
SK
(o)
Parameter
Propagation Delay
Ax to xYx
Propagation Delay
CLK to xYx
Propagation Delay
SEL to xYx
Output Enable Time
OEx to xYx
Output Disable Time
OEx to xYx
Pulse Duration, CLK HIGH or LOW
Setup Time, Ax data before CLK↑
Hold Time, Ax data after CLK↑
Output Skew
(2)
(1)
V
CC
= 2.5V ± 0.2V
Min
.
150
1.1
1
1.1
1
1.4
3.3
2
0.7
Max.
—
4.7
5.3
6
5.9
6.3
—
—
—
3.3
2
0.5
V
CC
= 2.7V
Min
.
150
Max.
—
4.8
5.3
6.2
5.9
5.4
—
—
—
V
CC
= 3.3V ± 0.3V
Min
.
150
1.5
1.4
1.5
1.1
1.6
3.3
1.6
1.1
Max.
—
4.3
4.7
4.8
5.1
5.1
—
—
—
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH162832
3.3V CMOS 1-BIT TO 2-BIT ADDRESS REGISTER/DRIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
NEW16link
SAM E PHAS E
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORM ALLY
CLOSE D
LOW
t
PZH
OUTPUT
SW ITCH
NORM ALLY
OPEN
HIGH
V
LOAD /2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD /2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LOAD
Open
GND
V
IN
D.U.T.
V
OU T
R
T
500
Ω
C
L
ALV C Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
NEW16link
t
R EM
GND
Open
t
S U
t
H
OUTPUT SKEW -
INPUT
TSK
(x)
t
PH L1
V
IH
V
T
0V
V
OH
t
PLH1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
P LH1
or
t
PH L2
-
t
P HL1
ALV C Link
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
