DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P0016
4-BIT SINGLE-CHIP MICROCONTROLLER
The
µ
PD75P0016 replaces the
µ
PD750008’s internal mask ROM with a one-time PROM and features expanded
ROM capacity.
Because the
µ
PD75P0016 supports programming by users, it is suitable for use in prototype testing for system
development using the
µ
PD750004, 750006, or 750008 products, and for use in small-lot production.
Detailed information about product features and specifications can be found in the following document
µ
PD750008 User's Manual: U10740E
FEATURES
•
Compatible with
µ
PD750008
•
Memory capacity:
• PROM : 16384
×
8 bits
• RAM
: 512
×
4 bits
•
Can operate in same power supply voltage as the mask ROM version
µ
PD750008
• V
DD
= 2.2 to 5.5 V
•
Supports QTOP™ microcontroller
Remark
QTOP Microcontroller is the general name for a total support service that includes imprinting, marking,
screening, and verifying one-time PROM single-chip microcontrollers offered by NEC.
ORDERING INFORMATION
Part number
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10
×
10 mm, 0.8-mm pitch)
ROM (× 8 bits)
16384
16384
µ
PD75P0016CU
µ
PD75P0016GB-3BS-MTX
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U10328EJ3V1DS00 (3rd edition)
Date Published August 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995
µ
PD75P0016
FUNCTION LIST
Item
Instruction execution time
Function
• 0.95, 1.91, 3.81, 15.3
µ
s (main system clock: at 4.19 MHz operation)
• 0.67, 1.33, 2.67, 10.7
µ
s (main system clock: at 6.0 MHz operation)
• 122
µ
s (subsystem clock: at 32.768 kHz operation)
On-chip memory
PROM
RAM
General register
I/O port
CMOS input
CMOS I/O
N-ch open drain I/O
Total
Timer
16384
×
8 bits
512
×
4 bits
• In 4-bit operation: 8
×
4 banks
• In 8-bit operation: 4
×
4 banks
8
18
8
34
4 channels
•
•
•
•
Serial interface
8-bit timer/event counter: 1 channel
8-bit timer counter: 1 channel
Basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Connection of on-chip pull-up resistor specifiable by software: 7
Direct LED drive capability
Connection of on-chip pull-up resistor specifiable by software: 18
Direct LED drive capability
13 V withstand voltage
• 3-wire serial I/O mode ... Switching of MSB/LSB-first
• 2-wire serial I/O mode
• SBI mode
16 bits
•
Φ,
524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)
•
Φ,
750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)
• 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock:
at 32.768 kHz operation)
• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)
Bit sequential buffer (BSB)
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt
Test input
System clock oscillation circuit
Standby function
Operating ambient temperature
Supply voltage
Package
External: 3 Internal: 4
External: 1 Internal: 1
• Main system clock oscillation ceramic/crystal oscillation circuit
• Subsystem clock oscillation crystal oscillation circuit
STOP/HALT mode
T
A
= –40 to +85˚C
V
DD
= 2.2 to 5.5 V
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10
×
10 mm, 0.8-mm pitch)
2
Data Sheet U10328EJ3V1DS00
µ
PD75P0016
TABLE OF CONTENTS
1.
2.
3.
PIN CONFIGURATION ........................................................................................................................ 4
BLOCK DIAGRAM ............................................................................................................................. 6
PIN FUNCTIONS ................................................................................................................................ 7
3.1
3.2
3.3
3.4
Port Pins ..................................................................................................................................................... 7
Non-port Pins ............................................................................................................................................. 8
I/O Circuits for Pins ................................................................................................................................... 9
Handling of Unused Pins ........................................................................................................................ 11
4.
SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12
4.1
4.2
Differences between Mk I Mode and Mk II Mode ................................................................................... 12
Setting of Stack Bank Selection (SBS) Register ................................................................................... 13
5.
6.
7.
8.
DIFFERENCES BETWEEN
µ
PD75P0016 AND
µ
PD750004, 750006, AND 750008 ...................... 14
MEMORY CONFIGURATION ........................................................................................................... 15
INSTRUCTION SET .......................................................................................................................... 17
ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28
8.1
8.2
8.3
8.4
Operation Modes for Program Memory Write/Verify ............................................................................ 28
Steps in Program Memory Write Operation .......................................................................................... 29
Steps in Program Memory Read Operation ........................................................................................... 30
One-Time PROM Screening .................................................................................................................... 31
9.
ELECTRICAL SPECIFICATIONS ..................................................................................................... 32
10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46
11. PACKAGE DRAWINGS .................................................................................................................... 48
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50
APPENDIX A. FUNCTION LIST OF
µ
PD75008, 750008, 75P0016 ....................................................... 51
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 53
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 57
Data Sheet U10328EJ3V1DS00
3
µ
PD75P0016
1. PIN CONFIGURATION (Top View)
•
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µ
PD75P0016CU
XT1
XT2
RESET
X1
X2
P33/MD3
P32/MD2
P31/MD1
P30/MD0
P81
P80
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
P13/TI0
P12/INT2
P11/INT1
P10/INT0
V
PP
Note
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
P40/D0
P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
Note
Directly connect V
PP
to V
DD
in the normal operation mode.
•
44-pin plastic QFP (10
×
10 mm, 0.8-mm pitch)
µ
PD75P0016GB-3BS-MTX
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
V
DD
V
PP
Note
P10/INT0
P11/INT1
P12/INT2
NC
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
P53/D7
P52/D6
P51/D5
P50/D4
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P13/TI0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P80
P81
P30/MD0
P31/MD1
P32/MD2
P33/MD3
NC
P43/D3
P42/D2
P41/D1
P40/D0
V
SS
Note
Directly connect V
PP
to V
DD
in the normal operation mode.
4
Data Sheet U10328EJ3V1DS00
XT1
XT2
RESET
X1
X2
µ
PD75P0016
PIN IDENTIFICATIONS
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
P70-P73
P80, P81
KR0-KR7
V
DD
V
SS
V
PP
NC
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
: Port7
: Port8
: Key Return 0-7
: Positive Power Supply
: Ground
: Programming Power Supply
: No Connection
SCK
SI
SO
SB0, SB1
RESET
TI0
PTO0, PTO1
BUZ
PCL
INT0, 1, 4
INT2
X1, X2
XT1, XT2
MD0-MD3
D0-D7
: Serial Clock
: Serial Input
: Serial Output
: Serial Data Bus 0,1
: Reset
: Timer Input 0
: Programmable Timer Output 0, 1
: Buzzer Clock
: Programmable Clock
: External Vectored Interrupt 0, 1, 4
: External Test Input 2
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
: Mode Selection 0-3
: Data Bus 0-7
Data Sheet U10328EJ3V1DS00
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
