KM23V4000D(G)
4M-Bit (512Kx8) CMOS MASK ROM
FEATURES
•
524,288 x 8 bit organization
•
Fast access time
3.3V Operation : 100ns(Max.)
3.0V Operation : 120ns(Max.)
•
Supply voltage : single +3.0V/ single +3.3V
•
Current consumption
Operating : 25mA(Max.)
Standby : 30µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. KM23V4000D : 32-DIP-600
-. KM23V4000DG : 32-SOP-525
CMOS MASK ROM
GENERAL DESCRIPTION
The KM23V4000D(G) is a fully static mask programmable ROM
organized 524,288 x 8 bit. It is fabricated using silicon gate
CMOS process technology.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The KM23V4000D is packaged in a 32-DIP and the
KM23V4000DG in a 32-SOP.
FUNCTIONAL BLOCK DIAGRAM
A
18
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(524,288x8)
PIN CONFIGURATION
.
.
.
.
.
.
.
.
A
0
N.C
A
16
A
15
1
2
3
4
5
6
7
8
9
32 V
CC
31 A
18
30 A
17
29 A
14
28 A
13
27 A
8
Y
BUFFERS
AND
DECODER
SENSE AMP.
BUFFERS
A
12
A
7
A
6
A
5
A
4
. . .
CE
OE
A
3
DIP
&
SOP
26 A
9
25 A
11
24 OE
23 A
10
21 CE
21 Q
7
20 Q
6
19 Q
5
18 Q
4
17 Q
3
A
2
10
CONTROL
LOGIC
Q
0
Q
7
A
1
11
A
0
12
Q
0
Q
1
Q
2
13
14
15
Pin Name
A
0
- A
18
Q
0
- Q
7
CE
OE
V
CC
V
SS
N.C
Pin Function
Address Inputs
Data Outputs
Chip Enable
Output Enable
Power
Ground
No Connection
V
SS
16
KM23V4000D(G)
KM23V4000D(G)
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Symbol
V
IN
T
BIAS
T
STG
Rating
CMOS MASK ROM
Unit
V
°C
°C
-0.3 to +4.5
-10 to +85
-55 to +150
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70°C)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400µA
I
OL
=2.1mA
Test Conditions
CE=OE=V
IL
,
all outputs open
V
CC
=3.3±0.3V
V
CC
=3.0±0.3V
Min
-
-
-
-
-
-
2.0
-0.3
2.4
-
Max
25
20
500
30
10
10
V
CC
+0.3
0.6
-
0.4
Unit
mA
mA
µA
µA
µA
µA
V
V
V
V
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
CC
+0.3V which, during transitions, may overshoot to V
CC
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
OE
X
H
L
Mode
Standby
Operating
Operating
Data
High-Z
High-Z
Dout
Power
Standby
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
10
10
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
KM23V4000D(G)
CMOS MASK ROM
AC CHARACTERISTICS
(T
A
=0°C to+70°C, V
CC
=3.3V/3.0V
±
0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and C
L
=100pF
READ CYCLE
Item
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
Symbol
t
RC
t
ACE
t
AA
t
OE
t
DF
t
OH
0
V
CC
=3.3V±0.3V
Min
100
100
100
50
20
0
Max
V
CC
=3.0V±0.3V
Min
120
120
120
60
20
Max
Unit
ns
ns
ns
ns
ns
ns
TIMING DIAGRAM
READ
ADD
t
ACE
CE
t
OE
ADD1
t
RC
ADD2
t
DF(Note)
t
AA
OE
t
OH
D
OUT
VALID DATA
VALID DATA
NOTE :
t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
KM23V4000D(G)
PACKAGE DIMENSIONS
32-DIP-600
#32
#17
CMOS MASK ROM
(Unit : mm/inch)
+0.10
-0.05
+0.004
0.010
-0.002
0.25
13.60±
0.20
0.535±
0.008
#1
42.31
1.666 MAX
4.191±
0.20
1.650±
0.008
#16
3.81±
0.20
0.150±
0.008
5.08
0.200 MAX
15.24
0.600
0~15°
( 1.91 )
0.075
0.46±
0.10
0.018±
0.004
1.52±
0.10
0.060±
0.004
2.54
0.100
0.38
MIN
0.015
3.30±
0.30
0.130±
0.012
KM23V4000D(G)
PACKAGE DIMENSIONS
32-SOP-525
#32
#17
CMOS MASK ROM
(Unit : mm/inch)
0~8°
14.12±
0.30
11.43±
0.20
0.556±
0.012
0.450±
0.008
13.34
0.525
#1
#16
0.20
+0.10
-0.05
0.008
+0.004
-0.002
2.74±
0.20
0.108±
0.008
3.00
0.118 MAX
0.10 MAX
0.004 MAX
0.80±
0.20
0.031±
0.008
20.87
0.822 MAX
20.47±
0.20
0.806±
0.008
0.71
( 0.028 )
+0.100
-0.050
0.016
+0.004
-0.002
0.41
1.27
0.050
0.05
0.002 MIN
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