DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD784224, 784225, 784224Y, 784225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
The
µ
PD784224 and 784225 are products of the
µ
PD784225 Subseries in the 78K/IV Series. Besides a high-
speed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A
converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral
hardware.
The
µ
PD784224Y and 784225Y are based on the
µ
PD784225 Subseries with the addition of a multimaster-
supporting I
2
C bus interface.
Flash memory versions, the
µ
PD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM
version with flash memory, and various development tools are also available.
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when
designing your system.
µ
PD784225, 784225Y Subseries User’s Manual - Hardware : U12697E
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
• I
2
C bus
• ROM correction
• Inherits peripheral functions of
µ
PD780058Y
Subseries
• Minimum instruction execution time
160 ns (main system clock f
XX
= 12.5 MHz)
61
µ
s (subsystem clock f
XT
= 32.768 kHz)
• I/O port: 67 pins
• Timer/counter: 16-bit timer/counter
×
1 unit
8-bit timer/counter
×
4 units
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, multi-master supporting I
2
C
bus
Note
): 1 channel
Note
µ
PD784225Y Subseries only
• Standby function
HALT/STOP/IDLE mode
In power-saving mode: HALT/IDLE mode (with
subsystem clock)
• Clock division function
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• Clock output function
f
XX
, f
XX
/2, f
XX
/2
2
, f
XX
/2
3
, f
XX
/2
4
, f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
, f
XT
selectable
• Buzzer output function
f
XX
/2
10
, f
XX
/2
11
, f
XX
/2
12
, f
XX
/2
13
selectable
• A/D converter: 8-bit resolution
×
8 channels
• D/A converter: 8-bit resolution
×
2 channels
• Supply voltage: V
DD
= 1.8 to 5.5 V
APPLICATION FIELD
Car audio, portable audio, telephones, etc.
Unless contextually excluded, references in this document to
µ
PD784225 mean
µ
PD784224, 784225, 784224Y,
and 784225Y.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Document No. U12376EJ1V0DS00 (1st edition)
Date Published May 2000 J CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µ
PD784224, 784225, 784224Y, 784225Y
ORDERING INFORMATION
Part Number
Package
80-pin
80-pin
80-pin
80-pin
80-pin
80-pin
80-pin
80-pin
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
QFP (14
×
14 mm)
TQFP (fine pitch) (14
QFP (14
×
14 mm)
TQFP (fine pitch) (14
QFP (14
×
14 mm)
TQFP (fine pitch) (14
QFP (14
×
14 mm)
TQFP (fine pitch) (14
×
20 mm)
×
20 mm)
×
20 mm)
×
20 mm)
Internal ROM (Bytes) Internal RAM (Bytes)
96 K
96 K
128 K
128 K
96 K
96 K
128 K
128 K
3,584
3,584
4,352
4,352
3,584
3,584
4,352
4,352
µ
PD784224GC-×××-8BT
µ
PD784224GK-×××-9EU
Note
µ
PD784225GC-×××-8BT
µ
PD784225GK-×××-9EU
µ
PD784224YGC-×××-8BT
µ
PD784224YGK-×××-9EU
µ
PD784225YGC-×××-8BT
Note
µ
PD784225YGK-×××-9EU
Note
Note
Under development
Remark
×××
indicates a ROM code suffix.
2
Data Sheet U12376EJ1V0DS00
µ
PD784224, 784225, 784224Y, 784225Y
78K/IV SERIES LINEUP
: In mass production
: Under development
Supports I
2
C bus
Supports multi-master I
2
C bus
µ
PD784038Y
µ
PD784038
µ
PD784225Y
µ
PD784225
80-pin, ROM correction added
Supports multi-master I
2
C bus
Standard models
µ
PD784026
Enhanced
A/D converter,
16-bit timer, and
power management
Enhanced internal memory capacity
Pin-compatible with the
µ
PD784026
Supports multi-master I
2
C bus
µ
PD784216AY
µ
PD784216A
100-pin, enhanced I/O and
internal memory capacity
µ
PD784218AY
µ
PD784218A
Enhanced internal memory
capacity, ROM correction added
µ
PD784054
µ
PD784046
ASSP models
µ
PD784956A
For DC inverter control
On-chip 10-bit A/D converter
µ
PD784938A
Enhanced functions of the
µ
PD784908, enhanced
internal memory capacity,
ROM correction added.
Supports multi-master I
2
C bus
µ
PD784908
On-chip IEBus
TM
controller
µ
PD784928Y
µ
PD784915
Software servo control
On-chip analog circuit for VCRs
Enhanced timer
µ
PD784928
Enhanced functions
of the
µ
PD784915
µ
PD784967
On-chip FIP controller/driver
Data Sheet U12376EJ1V0DS00
3
µ
PD784224, 784225, 784224Y, 784225Y
FUNCTIONS
Part Number
Item
Number of basic instructions
(mnemonics)
General-purpose register
Minimum instruction execution
time
Internal
memory
Memory space
I/O port
Total
CMOS Input
CMOS I/O
Pins with
ancillary
Pins with pull-up
resistor
ROM
RAM
113
8 bits
×
16 registers
×
8 banks, or 16 bits
×
8 registers
×
8 banks (memory mapping)
• 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: f
XX
= 12.5 MHz)
• 61
µ
s (subsystem clock: f
XT
= 32.768 kHz)
96 Kbytes
3,584 bytes
67
8
59
57
16
4 bits
×
2, or 8 bits
×
1
Timer/event counter
(16-bit)
: Timer counter
×
1
Capture/compare register
×
2
Pulse output
• PWM/PPG output
• Square wave output
• One-shot pulse output
Pulse output
• PWM output
• Square wave output
Pulse output
• PWM output
• Square wave output
128 Kbytes
4,352 bytes
µ
PD784224,
µ
PD784224Y
µ
PD784225,
µ
PD784225Y
1 MB with program and data spaces combined
functions
Note 1
LEDs direct
drive output
Real-time output port
Timer
Timer/event counter 1 : Timer counter
×
1
(8-bit)
Compare register
×
1
Timer/event counter 2 : Timer counter
×
1
(8-bit)
Compare register
×
1
Timer 5
(8-bit)
Timer 6
(8-bit)
Serial interface
A/D converter
D/A converter
Clock output
Buzzer output
Watch timer
Watchdog timer
Standby
Interrupt
Hardware
Software
Non-maskable
Maskable
: Timer counter
×
1
Compare register
×
1
: Timer counter
×
1
Compare register
×
1
• UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
• CSI (3-wire serial I/O, I
2
C bus
Note 2
supporting multi master): 1 channel
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
Selectable from f
XX
, f
XX
/2, f
XX
/2
2
, f
XX
/2
3
, f
XX
/2
4
, f
XX
/2
5
, f
XX
/2
6
, f
XX
/2
7
, f
XT
Selectable from f
XX
/2
10
, f
XX
/2
11
, f
XX
/2
12
, f
XX
/2
13
1 channel
1 channel
• HALT/STOP/IDLE mode
• In power-saving mode (with subsystem clock): HALT/IDLE mode
25 (internal: 18, external: 7)
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 17, external: 6
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage
Package
V
DD
= 1.8 to 5.5 V
• 80-pin plastic QFP(14
×
14 mm)
• 80-pin plastic TQFP (fine pitch) (12
×
12 mm)
Notes 1.
The pins with ancillary functions are included in the I/O pins.
2.
µ
PD784225Y Subseries only
4
Data Sheet U12376EJ1V0DS00
µ
PD784224, 784225, 784224Y, 784225Y
CONTENTS
1.
2.
DIFFERENCES AMONG MODELS IN
µ
PD784225, 784225Y SUBSERIES .............................. 7
MAJOR DIFFERENCES BETWEEN
µ
PD784216Y SUBSERIES AND
µ
PD780058Y SUBSERIES ............................................................................................................. 8
PIN CONFIGURATION (Top View) ............................................................................................... 9
BLOCK DIAGRAM ........................................................................................................................ 11
PIN FUNCTION ............................................................................................................................... 12
5.1
5.2
5.3
Port Pins ................................................................................................................................................ 12
Pins Other Than Port Pins .................................................................................................................. 14
I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16
3.
4.
5.
6.
CPU ARCHITECTURE ................................................................................................................... 20
6.1
6.2
Memory Space ...................................................................................................................................... 20
CPU Registers ...................................................................................................................................... 23
6.2.1
6.2.2
6.2.3
General-purpose registers .......................................................................................................... 23
Control registers .......................................................................................................................... 24
Special function registers (SFRs) ............................................................................................... 25
7.
PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Ports ....................................................................................................................................................... 30
Clock Generator ................................................................................................................................... 31
Real-Time Output Port ......................................................................................................................... 33
Timer ...................................................................................................................................................... 34
A/D Converter ....................................................................................................................................... 37
D/A Converter ....................................................................................................................................... 38
Serial Interface ..................................................................................................................................... 39
7.7.1
7.7.2
7.8
7.9
Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40
Clocked serial interface (CSI) ..................................................................................................... 42
Clock Output Function ........................................................................................................................ 43
Buzzer Output Function ...................................................................................................................... 44
7.10 Edge Detection Function .................................................................................................................... 44
7.11 Watch Timer .......................................................................................................................................... 44
7.12 Watchdog Timer ................................................................................................................................... 45
8.
INTERRUPT FUNCTION ................................................................................................................ 46
8.1
8.2
8.3
8.4
8.5
Interrupt Sources ................................................................................................................................. 46
Vectored Interrupt ................................................................................................................................ 48
Context Switching ................................................................................................................................ 49
Macro Service ....................................................................................................................................... 49
Application Example of Macro Service ............................................................................................. 50
Data Sheet U12376EJ1V0DS00
5
51单片机
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