DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD8862
(2700 + 2700) PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The
µ
PD8862 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD8862 has 3 rows of (2700 + 2700) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Line spacing
•
Color filter
•
Resolution
: (2700 + 2700) staggered pixels
×
3
: 5.25
µ
m
: 63
µ
m (12 lines) Red line - Green line, Green line - Blue line
10.5
µ
m (2 lines) Odd line - Even line (for each color)
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 24 dot/mm A4 (210
×
297 mm) size (shorter side)
600 dpi US letter (8.5”
×
11”) size (shorter side)
•
Drive clock level : CMOS output under 5 V operation
•
Data rate
•
Power supply
•
On-chip circuits
: 6 MHz Max.
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
7
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
µ
PD8862CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16033EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2002
µ
PD8862
BLOCK DIAGRAM
V
OD
19
GND
11
φ
2L
17
φ
2
15
φ
1
14
CCD analog shift register
Transfer gate
D14
D66
D68
D70
S5400
13
D69
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
D67
D14
D66
D68
D70
S5400
S2
V
OUT
1
20
(Blue)
······
Photocell
(Blue)
D67
S5399
φ
TG1
(Blue)
S1
12
D69
S2
V
OUT
2
21
(Green)
······
Photocell
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
D67
D14
D66
D68
D70
S5400
S5399
φ
TG2
(Green)
S1
10
D69
Transfer gate
CCD analog shift register
3
2
4
S2
V
OUT
3
22
(Red)
······
Photocell
(Red)
S5399
φ
TG3
(Red)
S1
8
9
φ
CLB
φ
RB
φ
1L
φ
2
φ
1
2
Data Sheet S16033EJ3V0DS
µ
PD8862
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
•
µ
PD8862CY
No connection
Reset gate clock
Reset feed-through level clamp clock
Last stage shift register clock 1
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 3
(for Red)
Ground
NC
1
2
22
21
V
OUT
3
V
OUT
2
V
OUT
1
V
OD
NC
Output signal 3 (Red)
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
No connection
Last stage shift register clock 2
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
φ
RB
1
1
φ
CLB
φ
1L
NC
NC
NC
3
4
5
6
7
8
9
10
11
1
20
19
18
17
16
15
14
13
12
Green
Blue
Red
φ
2L
NC
φ
2
φ
2
φ
1
φ
1
φ
TG1
φ
TG2
5400
5400
GND
Caution Connect the No connection pins (NC) to GND.
5400
φ
TG3
Data Sheet S16033EJ3V0DS
3
µ
PD8862
PHOTOCELL STRUCTURE DIAGRAM
2.75
µ
m
2.5
µ
m
5.25
µ
m
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Blue photocell array
Blue photocell array
2 lines
(10.5
µ
m)
10 lines
(52.5
µ
m)
12 lines
(63
µ
m)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Green photocell array
Green photocell array
2 lines
(10.5
µ
m)
10 lines
(52.5
µ
m)
12 lines
(63
µ
m)
5.25
µ
m
5.25
µ
m
5.25
µ
m
Red photocell array
Red photocell array
2 lines
(10.5
µ
m)
4
Data Sheet S16033EJ3V0DS
µ
PD8862
ABSOLUTE MAXIMUM RATINGS (T
A
=
+25°C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock
voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Note
Symbol
V
OD
V
φ
1
, V
φ
2
, V
φ
1L
, V
φ
2L
V
φ
RB
V
φ
CLB
Ratings
−0.3
to
+15
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
0 to
+60
−40
to
+70
Unit
V
V
V
V
V
φ
TG1
to V
φ
TG3
T
A
T
stg
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+25°C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock
high level
Reset feed-through level clamp clock
low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
RB
4.75
−0.3
−
V
φ
1_H
0
2.0
Note
Symbol
V
OD
V
φ
1_H
, V
φ
2_H
, V
φ
1LH
, V
φ
2LH
V
φ
1_L
, V
φ
2_L
, V
φ
1LL
, V
φ
2LL
V
φ
RBH
V
φ
RBL
V
φ
CLBH
Min.
11.4
4.75
−0.3
4.5
−0.3
4.5
−0.3
Typ.
12.0
5.0
0
5.0
0
5.0
Max.
12.6
5.5
+0.25
5.5
+0.5
5.5
+0.5
V
φ
1_H
Note
Unit
V
V
V
V
V
V
V
φ
CLBL
0
V
V
V
MHz
+0.15
6.0
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1_H
),
Image lag can increase.
Data Sheet S16033EJ3V0DS
5
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