DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD98411
ATM QUAD SONET FRAMER
The
µ
PD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a
transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-
3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer,
and a reception function to separate the overhead and ATM cell from the data string received from the PMD device
and transmit the ATM cell to the ATM layer.
The
µ
PD98411 NEASCOT-P40 combines these transmission
This LSI is ideally suited for
/reception functions into a port function that is realized as a single 4-port LSI chip.
use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.
In addition, the
µ
PD98411 also has a clock recovery function for each port to extract synchronous clock for
reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.
For the details of functional description, refer to the following user's manual.
µ
PD98411 User's Manual : S12736E
FEATURES
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•
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Incorporates an ATM user network interface TC sublayer function for four channels.
Conforms to ATM FORUM UNI v3.1.
Incorporates four clock recovery PLLs and one clock synthesizer PLL.
Conforms to ATM FORUM UTOPIA Level 2 v1.0.
•
ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.
Single 16-bit
Single 8-bit
Dual 8-bit
1TCLAV/1RCLAV (Cell Available signal mode)
Direct Status Indication mode
Multiplexed Status Polling mode
•
A management interface can be set to either of two modes.
RD-WR-RDY style (Intel-compatible mode)
DS-R/W-ACK style (Motorola-compatible mode)
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•
•
•
•
The line-side PMD interface accepts a P-ECL level input.
Supports a loopback function.
Supports a pseudo error generation frame transmission function.
Incorporates one general input port per channel and three output ports (each able to drive an LED) per
channel.
Supports JTAG boundary scan test (IEEE 1149.1).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12953EJ4V0DS00 (4th edition)
Date Published January 1999 NS CP(K)
Printed in Japan
©NEC
Corporation 1997,1999
µ
PD98411
•
Incorporates a wide range of operation, administration, and maintenance (OAM) functions.
Transmission
Alarm Condition and Failure Detection
APS
Line AIS/Path AIS
Line RDI/Path RDI
Line Quality Monitoring
Insertion of B1-byte computation
Insertion of B2-byte computation
Insertion of B3-byte computation
Automatic transmission of a Line REI
Automatic transmission of a Path REI
Reception
Alarm Condition and Failure Detection
External input signal change
LOS
OOF
LOF
LOP
OCD
LCD
Line AIS/Path AIS
Line RDI/Path RDI
APS
Notification of Degraded Line Quality
B1 error
B2 error
B3 error
Line REI
Path REI
Frequency justification
FIFO overflow
Line Quality Monitor Counter
B1 error counter
B2 error counter
B3 error counter
Line REI counter
Path REI counter
Frequency justification counter
HEC processing dropped cell counter
FIFO overflow dropped cell counter
Received idle cell counter
Valid cell counter
•
•
0.35-
µ
m CMOS process
Low power consumption; +3.3 V single-voltage power supply
ORDERING INFORMATION
Part Number
Package
240-pin plastic QFP (fine pitch) (32
×
32 mm)
µ
PD98411GN-MMU
2
Data Sheet S12953EJ4V0DS00
µ
PD98411
APPLICATIONS
The following are examples of the application using the
µ
PD98411.
•
ATM Switches
NIC
µ
PD98411
155 ATM Interface
OC-12
SONET Framer
µ
PD98411
NIC
SWITCH
Backbone
Network
µ
PD98411
NIC
µ
PD98411
UTOPIA Level2
CPU
Data Sheet S12953EJ4V0DS00
3
µ
PD98411
SYSTEM CONFIGURATION
1)
µ
PD98411 System Application
PMD I/F
(PECL)
Status
OSC
(19.44M)
Optical
Module
Multimode Fiber
µ
PD98411
ATM Layer Device
Tx UTOPIA I/F
Optical
Module
(NEASCOT-P40)
Equalizer
Components
Magnetics
RJ-45
Connector
Shielded Twist Pair
Rx UTOPIA I/F
Management I/F
Equalizer
Components
Magnetics
RJ-45
Connector
Processor
2) Connection to 5-V transceiver/receiver
The following show an example of connecting the
µ
PD98411 to a 5-V optical transceiver. Since the
µ
PD98411 operates on 3.3 V, a coupling circuit should be added if it is to be connected to a 5-V device.
µ
PD98411
Port0
3.3V
0.1
µ
F
510Ω 510Ω 110Ω 110Ω
82Ω
5V
82Ω 430Ω 430Ω
GND
RDIT0
RDIC0
TDOT0
TDOC0
820Ω 820Ω
91Ω
91Ω
5V optical transceiver
RSDT
RSDC
TXDT
TXDC
0.1
µ
F×4
5V
130Ω 130Ω 1.1kΩ 1.1kΩ
0.1
µ
F
GND
SD0
PECL->TTL
translator
MC10H350 by
Motorola, etc.
GND
GND
VCCR
VCCT
VEER
VEET
SD
4
Data Sheet S12953EJ4V0DS00
µ
PD98411
3) UTOPIA Interface
The UTOPIA interface transfers transmit/receive cell data to a device in the upper ATM layer.
version 1.0 June ’95” standard.
Bus Mode
Dual eight-bit bus.
In this mode, an 8-bit data bus is used for two ports. Ports 0
and 1 transfer signals using one eight-bit bus, while ports 2
and 3 transfer signals using another eight-bit bus. The ports
operate independently.
The way to indicate Cell Available state
One TCLAV & one RCLAV signal mode
The one TCLAV & one RCLAV signal mode outputs the TCLAV
and RCLAV signal status information for four ports of the
µ
PD98411 by multiplexing them into a single signal.
µ
PD98411
Port0
TCLAV
RCLAV
Port1
TDI
The interface
between the
µ
PD98411 and the ATM layer conforms to “MPHY Data Path Operation” of the “UTOPIA Level 2
PMD
µ
PD98411
Port0
UTOPIA
8-bit
ATM layer
device
Port1
ATM layer
Device
Port2
8-bit
Port3
ATM layer
device
Port2
8 or 16-bit
RDO
Port3
TADD
RADD
Single eight-bit bus.
In this mode, cell data for all four ports is transferred through
an eight-bit bus. The maximum transfer rate is 400 Mbps
(8 bits x 50 MHz).
Direct Status Indication Mode
µ
PD98411 has four TXCLAV and RXCLAV status signals, one
pair of TXCLAV and RXCLAV for each port. Status signals and
cell transfers are independent of each other. No address
information is needed to obtain status information.
PMD
µ
PD98411
Port0
Port1
UTOPIA
Port0
TCLAV3-TCLAV0
Port1
8-bit
Port2
Port3
ATM layer
device
µ
PD98411
Port2
RCLAV3-RCLAV0
TDI
8 or 16-bit
RDO
ATM layer
Device
Port3
TADD
RADD
Single sixteen-bit bus.
In this mode, cell data for all four ports is transferred through
a sixteen-bit bus. The maximum transfer rate is 800 Mbps
(16 bits x 50 MHz).
Multiplexed Status Polling Mode
When six or more
µ
PD98411s are connected to one ATM layer,
ATM layer obtain the status information of all the connected
ports in the 53 clock cycles in which it transmits or receives a
PMD
µ
PD98411
Port0
Port1
single data cell. Because a minimum of two clock cycles are
UTOPIA
required to obtain the TCLAV/RCLAV signal status of a port by
ATM layer polling. Therefore every port address is allocated in a
fixed manner to one of the four status signals and to one of eight
16-bit
Port2
Port3
ATM layer
device
port groups.
Data Sheet S12953EJ4V0DS00
5
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