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SY10E160JZTR

产品描述Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28
产品类别逻辑    逻辑   
文件大小60KB,共5页
制造商Micrel ( Microchip )
官网地址https://www.microchip.com
标准
下载文档 详细参数 选型对比 全文预览

SY10E160JZTR概述

Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28

SY10E160JZTR规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Micrel ( Microchip )
零件包装代码QLCC
包装说明QCCJ,
针数28
Reach Compliance Codecompliant
系列10E
JESD-30 代码S-PQCC-J28
JESD-609代码e3
长度11.48 mm
逻辑集成电路类型PARITY GENERATOR/CHECKER
湿度敏感等级2
位数12
功能数量1
端子数量28
最高工作温度85 °C
最低工作温度
输出极性COMPLEMENTARY
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
峰值回流温度(摄氏度)260
传播延迟(tpd)0.95 ns
认证状态Not Qualified
座面最大高度4.57 mm
表面贴装YES
技术ECL
温度等级COMMERCIAL EXTENDED
端子面层Matte Tin (Sn)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度11.48 mm

文档预览

下载PDF文档
Micrel, Inc.
12-BIT PARITY
GENERATOR/CHECKER
SY10E160
SY100E160
SY10E160
SY100E160
FEATURES
s
Provides odd-HIGH parity of 12 inputs
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
Output register with Shift/Hold capability
s
900ps max. D to Q, /Q output
s
Enable control
s
Asynchronous Register Reset
s
Differential outputs
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E160
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E160 are high-speed, 12-bit parity
generator/checkers with differential outputs, for use in
new, high-performance ECL systems. The output Q takes
on a logic HIGH value only when an odd number of inputs
are at a logic HIGH. A logic HIGH on the enable input (EN)
forces the output Q to a logic LOW.
An additional feature of the E160 is the output register.
Two multiplexers and their associated signals control the
register input by providing the option of holding present
data, loading the new parity data or shifting external data
in. To hold the present data, the Hold signal (HOLD) must
be at a logic LOW level. If the HOLD signal is at a logic
HIGH, the data present at the Q output is passed through
the first multiplexer. Taking the Shift signal (SHIFT) to a
logic HIGH will shift the data at the S-IN pin into the output
register. If the SHIFT signal is at a logic LOW, the output
of the first multiplexer is then passed through to the register.
The register itself is clocked on the rising edge of CLK
1
or CLK
2
(or both). The presence of a logic HIGH on the
reset pin (R) forces the register output Y to a logic LOW.
BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
EN
HOLD
S-IN
SHIFT
CLK
1
CLK
2
R
Q
Q
0
MUX
1
SEL
1
SEL
R
0
MUX
Y
D
Y
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
Rev.: F
Amendment: /0
1
Issue Date: March 2006

SY10E160JZTR相似产品对比

SY10E160JZTR SY100E160JZTR
描述 Parity Generator/Checker, 10E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28 Parity Generator/Checker, 100E Series, 12-Bit, Complementary Output, ECL, PQCC28, LEAD FREE, PLASTIC, LCC-28
厂商名称 Micrel ( Microchip ) Micrel ( Microchip )
零件包装代码 QLCC QLCC
包装说明 QCCJ, QCCJ,
针数 28 28
Reach Compliance Code compliant unknown
系列 10E 100E
JESD-30 代码 S-PQCC-J28 S-PQCC-J28
JESD-609代码 e3 e3
长度 11.48 mm 11.48 mm
逻辑集成电路类型 PARITY GENERATOR/CHECKER PARITY GENERATOR/CHECKER
位数 12 12
功能数量 1 1
端子数量 28 28
最高工作温度 85 °C 85 °C
输出极性 COMPLEMENTARY COMPLEMENTARY
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 QCCJ QCCJ
封装形状 SQUARE SQUARE
封装形式 CHIP CARRIER CHIP CARRIER
传播延迟(tpd) 0.95 ns 0.95 ns
认证状态 Not Qualified Not Qualified
座面最大高度 4.57 mm 4.57 mm
表面贴装 YES YES
技术 ECL ECL
温度等级 COMMERCIAL EXTENDED COMMERCIAL EXTENDED
端子面层 Matte Tin (Sn) MATTE TIN
端子形式 J BEND J BEND
端子节距 1.27 mm 1.27 mm
端子位置 QUAD QUAD
宽度 11.48 mm 11.48 mm

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