Features:
◆
◆
◆
HIGH-SPEED 1.8V
256/128K x 36
IDT70P3519/99
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V/2.5V/1.8V INTERFACE
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
Low Power
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)
– Industrial: 3.6ns (166MHz)
Selectable Pipelined or Flow-Through output mode
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆
◆
◆
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
R/W
L
CE
0L
CE
1L
1
0
OE
L
FT/PIPE
L
T
O
N
CLK
L
1/0
D
E
D S
N N
E IG
M S
M E
O D
C W
E E
R N
◆
◆
◆
◆
0d 1d
d
Counter enable and repeat features
Interrupt and Collision Detection Flags
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
1.8V (±100mV) power supply for core
LVTTL compatible,1.8V to 3.3V power supply for I/Os and
control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
R
O
F
BE
3R
BE
2R
BE
1R
BE
0R
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
R
1
CE
0R
CE
1R
0
B B
WW
0 1
L L
B B
B
WW
W
2 3
3
L L
R
B
W
2
R
B B
WW
1 0
RR
1/0
OE
R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
0/1
0a 1a 0b 1b 0c 1c 0d 1d
0/1
,
FT/PIPE
R
abcd
dcba
256/128K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
R
A
17L(1)
A
17R(1)
,
A
0L
REPEAT
L
ADS
L
CNTEN
L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
TDI
CE
0 L
CE1L
R/
W
L
INTERRUPT
COLLISION
DETECTION
LOGIC
CE
0 R
CE1R
R/
W
R
JTAG
TDO
COL
R
INT
R
TCK
TMS
TRST
COL
L
INT
L
ZZ
L
(2)
NOTES:
1. Address A
17
is a NC for the IDT70P3599.
+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
ZZ
CONTROL
LOGIC
ZZ
R
(2)
7144 drw 01
JUNE 2009
DSC 7144/3
1
©2009 Integrated Device Technology, Inc.
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70P3519/99 is a high-speed 256/128K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times. With an input data register, the
IDT70P3519/99 has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70P3519/99 can support an operating voltage of 3.3V, 2.5V or
1.8V on one or both ports. The power supply for the core of the device
(V
DD
) is 1.8V.
T
O
N
D
E
D S
N N
E IG
M S
M E
O D
C W
E E
R N
R
O
F
6.42
2
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(2,3,4)
70P3519/99BC
BC-256
(5)
256-Pin BGA
Top View
(6)
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
02/12/08
A1
A15
NC
B1
TDI
B2
NC
B3
A
17L
(1)
B4
A
14L
B5
A
11L
B6
A
8L
B7
BE
2L
B8
CE
1L
B9
OE
L
B10
CNTEN
L
A
5L
B11
B12
A
2L
B13
A
0L
B14
B15
I/O
18L
C1
NC
C2
TDO
C3
NC
C4
A
15L
C5
A
12L
C6
A
9L
C7
BE
3L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
I/O
18R
I/O
19L
D1
D2
V
SS
D3
D4
I/O
20R
I/O
19R
I/O
20L
PIPE/
FT
L
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
I/O
15R
I/O
15L
I/O
16R
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
I/O
21R
I/O
21L
I/O
22L
V
DDQL
F1
F2
F3
F4
I/O
23L
I/O
22R
I/O
23R
V
DDQL
V
DD
G1
G2
G3
G4
G5
I/O
24R
I/O
24L
I/O
25L
V
DDQR
V
SS
H1
H2
H3
H4
H5
I/O
26L
I/O
25R
I/O
26R
V
DDQR
V
SS
J1
J2
J3
J4
J5
I/O
27L
I/O
28R
I/O
27R
V
DDQL
ZZ
R
K1
K2
K3
K4
K5
I/O
29R
I/O
29L
I/O
28L
V
DDQL
V
SS
L1
L2
L3
L4
L5
I/O
30L
I/O
31R
I/O
30R
V
DDQR
V
DD
M1
M2
M3
M4
M5
I/O
32R
I/O
32L
I/O
31L
V
DDQR
NOTES:
1. Pin is a NC for IDT70P3599.
2. All V
DD
pins must be connected to 1.8V power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
T
O
N
P1
P2
P3
R1
R2
R3
N1
N2
N3
N4
I/O
33L
I/O
34R
I/O
33R
PIPE/
FT
R
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DD
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
I/O
35R
I/O
34L
TMS
I/O
35L
NC
NC
TRST
D
E
D S
N N
E IG
M S
M E
O D
C W
E E
R N
C15
A
16L
A
13L
A
10L
A
7L
BE
1L
BE
0L
CLK
L
ADS
L
D9
D10
D11
A
6L
A
3L
NC
I/O
17R
I/O
16L
D16
R
O
F
A16
NC
NC
NC
B16
I/O
17L
C16
D5
D6
D7
D8
D12
D13
D14
D15
V
DD
V
DD
NC
INT
L
V
SS
V
SS
V
SS
V
DD
V
DD
V
DDQR
I/O
13L
I/O
14L
I/O
14R
F13
F14
F15
F16
F5
F6
F7
F8
F9
F10
F11
F12
COL
L
V
SS
V
SS
V
SS
V
SS
V
DD
V
DDQR
I/O
12R
I/O
13R
I/O
12L
G13
G14
G15
G16
G6
G7
G8
G9
G10
G11
G12
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQL
I/O
10L
I/O
11L
I/O
11R
H14
H15
H16
H6
H7
H8
H9
H10
H11
H12
H13
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQL
I/O
9R
J14
IO
9L
I/O
10R
J16
J6
J7
J8
J9
J10
J11
J12
J13
J15
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
L
V
DDQR
I/O
8R
I/O
7R
I/O
8L
K13
K14
K15
K16
K6
K7
K8
K9
K10
K11
K12
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
7L
L13
L14
L15
L16
L6
L7
L8
L9
L10
L11
L12
NC
COL
R
V
SS
M8
V
SS
V
SS
V
DD
V
DDQL
I/O
5L
M14
I/O
4R
I/O
5R
M16
M6
M7
M9
M10
M11
M12
M13
M15
V
DD
V
DD
INT
R
V
SS
V
SS
V
SS
V
DD
V
DD
V
DDQL
I/O
3R
I/O
3L
I/O
4L
N13
N14
N15
N16
N5
N6
N7
N8
N9
N10
N11
N12
I/O
2L
I/O
1R
I/O
2R
P16
P14
P15
A
16R
A
13R
A
10R
A
7R
BE
1R
BE
0R
CLK
R
ADS
R
R9
R10
R11
A
6R
A
3R
I/O
0L
I/O
0R
R15
I/O
1L
R16
R4
R5
R6
R7
R8
R12
R13
R14
NC
T4
A
15R
T5
A
12R
T6
A
9R
T7
BE
3R
CE
0R
R/W
R
REPEAT
R
A
4R
T8
T9
T10
T11
T12
A
1R
T13
NC
T14
NC
T15
NC
T16
,
T1
T2
T3
TCK
NC A
17R
(1)
A
14R
A
11R
A
8R
BE
2R
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
7144 drw 02d
,
6.42
3
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(2,3,4)
(con't.)
02/12/08
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
I/O
19L
I/O
18L
B1
B2
V
SS
B3
TDO
B4
COL
L
B5
A
16L
B6
A
12L
B7
A
8L
B8
BE
1L
B9
V
DD
B10
CLK
L
CNTEN
L
A
4L
B11
B12
B13
A
0L
B14
NC
B15
I/O
17L
B16
V
SS
B17
I/O
20R
V
SS
I/O
18R
C1
C2
C3
TDI A
17L
(1)
A
13L
C4
C5
C6
A
9L
C7
BE
2L
C8
CE
0L
C9
V
SS
C10
ADS
L
C11
A
5L
C12
A
1L
C13
NC
C14
V
DDQR
I/O
16L
I/O
15R
C15
C16
C17
V
DDQL
I/O
19R
V
DDQR
PL/
FT
L
INT
L
D1
D2
D3
D4
D5
A
14L
D6
A
10L
D7
BE
3L
CE
1L
D8
D9
V
SS
D10
R/W
L
D
11
A
6L
D12
A
2L
D13
V
DD
I/O
16R
I/O
15L
D14
D15
D16
I/O
22L
E1
V
SS
E2
I/O
21L
I/O
20L
A
15L
E3
E4
A
11L
A
7L
BE
0L
V
DD
OE
L
REPEAT
L
A
3L
V
DD
I/O
17R
V
DDQL
I/O
14L
I/O
14R
E14
E15
E16
E17
I/O
23L
I/O
22R
V
DDQR
I/O
21R
F1
F2
F3
F4
V
DDQL
I/O
23R
I/O
24L
G1
G2
G3
I/O
26L
V
SS
H1
H2
I/O
25L
I/O
24R
H3
H4
V
DD
I/O
26R
V
DDQR
I/O
25R
J1
J2
J3
J4
V
DDQL
V
DD
K1
K2
V
SS
K3
I/O
28R
L1
V
SS
L2
I/O
27R
V
SS
L3
L4
I/O
29R
I/O
28L
V
DDQR
I/O
27L
M1
M2
M3
M4
V
DDQL
I/O
29L
I/O
30R
V
SS
N1
N2
N3
N4
I/O
31L
P1
V
SS
I/O
31R
I/O
30L
P2
P3
P4
I/O
32R
I/O
32L
V
DDQR
I/O
35R
R1
R2
R3
R4
V
SS
T1
I/O
33L
I/O
34R
TCK A
17R
(1)
A
13R
T2
T3
T4
T5
T6
NOTES:
1. Pin is a NC for IDT70P3599.
2. All V
DD
pins must be connected to 1.8V power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
T
O
N
U1
U2
U3
I/O
33R
I/O
34L
V
DDQL
TMS
U4
V
SS
I/O
35L
PL/
FT
R
COL
R
A
15R
D
E
D S
N N
E IG
M S
M E
O D
C W
E E
R N
I/O
12L
I/O
13R
F15
F14
R
O
F
V
SS
D17
V
SS
I/O
13L
F16
F17
V
SS
V
SS
I/O
12R
I/O
11L
V
DDQR
G15
G16
G17
G4
G14
I/O
9L
V
DDQL
I/O
10L
I/O
11R
H15
H16
H17
70P3519/99BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
H14
V
DD
ZZ
L
I/O
9R
V
DD
V
SS
J16
I/O
10R
J17
J14
J15
ZZ
R
V
SS
V
DDQR
K16
K17
K4
K14
K15
I/O
7R
V
DDQL
I/O
8R
L15
L16
V
SS
L17
L14
I/O
6R
V
SS
I/O
7L
V
SS
M16
I/O
8L
M17
M14
M15
I/O
6L
I/O
5R
V
DDQR
N16
N17
N14
N15
I/O
3R
V
DDQL
I/O
4R
P15
P16
I/O
5L
P17
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
TRST
A
16R
R6
A
12R
A
9R
A
8R
BE
1R
V
DD
CLK
R
CNTEN
R
A
4R
R12
R13
I/O
2L
I/O
3L
R15
V
SS
R16
I/O
4L
R17
R5
R7
R8
R9
R10
R11
R14
BE
2R
CE
0R
T9
V
SS
ADS
R
A
5R
A
1R
NC
V
DDQL
I/O
0R
NC
I/O
1R
V
DDQR
T16
T17
T7
T8
T10
T11
T12
T13
T14
T15
INT
R
A
14R
A
10R
A
7R
BE
3R
CE
1R
U9
V
SS
R/W
R
A
6R
A
2R
V
SS
V
SS
U16
I/O
2R
U17
U5
U6
U7
U8
U10
U12
U13
U14
U15
A
11R
BE
0R
V
DD
OE
R
A
3R
A
0R
V
DD
I/O
0L
I/O
1L
7144 drw 02c
6.42
4
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
17L
(4)
I/O
0L
- I/O
35L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
BE
0L
-
BE
3L
V
DDQL
ZZ
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
INT
L
COL
L
INT
R
COL
R
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
17R
(4)
I/O
0R
- I/O
35R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
BE
0R
-
BE
3R
V
DDQR
ZZ
R
Names
Chip Enables (Input)
(5)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat
(2)
Byte Enables (9-bit bytes) (Input)
(5)
Power (I/O Bus) (3.3V, 2.5V or 1.8V)
(1)
(Input)
Sleep Mode pin
(3)
(Input)
Power (1.8V)
(1)
(Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
T
O
N
D
E
D S
N N
E IG
M S
M E
O D
C W
E E
R N
7144 tbl 01
R
O
F
NOTES:
1. V
DD
and V
DDQX
must be set to appropriate operating levels prior to applying inputs
on the I/Os and controls for that port.
2. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and the sleep mode pins themselves
(ZZx) are not affected during sleep mode.
4. Address A
17x
is a NC for the IDT70P3599.
5. Chip Enables and Byte Enables are double buffered when PL/FT = V
IH
, i.e., the
signals take two cycles to deselect.
6.42
5
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