Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 89HPES12NT3ZABC8

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89HPES12NT3ZABC8: 产品描述Bus Controller, PBGA324; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小495KB，共29页; 制造商IDT (Integrated Device Technology); 标准

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89HPES12NT3ZABC8概述

Bus Controller, PBGA324

89HPES12NT3ZABC8规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
包装说明	BGA, BGA324,18X18,40
Reach Compliance Code	compliant
JESD-30 代码	S-PBGA-B324
端子数量	324
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA324,18X18,40
封装形状	SQUARE
封装形式	GRID ARRAY
电源	1,3.3 V
认证状态	Not Qualified
表面贴装	YES
温度等级	COMMERCIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM

文档解析

这份文档是关于IDT公司生产的89HPES12NT3芯片的数据手册，该芯片属于IDT PRECISE™家族，是一种PCI Express®交换解决方案。以下是一些值得关注的技术信息：

产品概述：
- 89HPES12NT3是一款12通道、3端口的外围芯片，用于高性能应用，如服务器、存储和通信/网络。
主要特性：
- 提供高达48 Gbps（6 GBps）的聚合交换容量。
- 低延迟直通交换架构。
- 支持最大有效载荷大小高达2048字节。
- 符合PCI Express Base规范修订版1.0a。
灵活的架构：
- 支持多种配置选项，包括端口仲裁、端口链接宽度自动协商等。
- 支持非透明端口功能，包括交叉链路支持和映射窗口。
高度集成的解决方案：
- 无需外部组件，芯片内部集成了所需的所有功能。
可靠性、可用性和可服务性（RAS）特性：
- 支持热交换和故障转移应用。
电源管理：
- 支持PCI电源管理接口规范。
测试和调试特性：
- 内置SerDes伪随机比特流（PRBS）发生器，支持通过SMBus读取和写入任何内部寄存器。
SMBus接口：
- 包含两个SMBus接口，一个作为从设备提供对所有软件可见寄存器的访问，另一个作为主设备用于初始化。
引脚描述和特性：
- 文档提供了详细的引脚功能描述和特性，包括信号类型、名称、描述以及它们的内部上拉或下拉电阻情况。
系统时钟参数：
- 包括输入参考时钟频率范围、占空比、上升/下降时间等。
功耗：
- 提供了在不同条件下的典型和最大功耗数据。
直流电气特性：
- 包括PCIe传输和接收的电压、阻抗、眼图等参数。
封装信息：
- 芯片采用324球BGA封装，提供了详细的引脚分配图。
修订历史：
- 文档记录了数据手册的修订历史。
公司联系信息：
- 提供了IDT公司的联系方式和订购信息。

89HPES12NT3ZABC8文档预览

12-lane 3-Port Non-Transparent

PCI Express® Switch

89HPES12NT3

Data Sheet

Preliminary Information*

Device Overview

The 89HPES12NT3 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions offering the next-generation I/O inter-

connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip

that performs PCI Express Base switching with a feature set optimized

for high performance applications such as servers, storage, and commu-

nications/networking. It provides high-performance I/O connectivity and

switching functions between a PCIe® upstream port, a transparent

downstream port, and a non-transparent downstream port.

With non-transparent bridging (NTB) functionality, the PES12NT3

can be used standalone or as a chipset with IDT PCIe System Intercon-

nect Switches in multi-host and intelligent I/O applications such as

communications, storage, and blade servers where inter-domain

communication is required.

Features

◆

High Performance PCI Express Switch

–

Twelve PCI Express lanes (2.5Gbps), three switch ports

–

Delivers 48 Gbps (6 GBps) of aggregate switching capacity

–

Low latency cut-through switch architecture

–

Support for Max Payload size up to 2048 bytes

–

Supports one virtual channel and eight traffic classes

–

PCI Express Base specification Revision 1.0a compliant

Flexible Architecture with Numerous Configuration Options

–

Port arbitration schemes utilizing round robin

–

Supports automatic per port link width negotiation (x4, x2, or

x1)

–

Static lane reversal on all ports

–

Automatic polarity inversion on all lanes

–

Supports locked transactions, allowing use with legacy soft-

ware

–

Ability to load device configuration from serial EEPROM

–

Ability to control device via SMBus

◆

Non-Transparent Port

–

Crosslink support on NTB port

–

Four mapping windows supported

•

Each may be configured as a 32-bit memory or I/O window

•

May be paired to form a 64-bit memory window

–

Interprocessor communication

•

Thirty-two inbound and outbound doorbells

•

Four inbound and outbound message registers

•

Two shared scratchpad registers

–

Allows up to sixteen masters to communicate through the non-

transparent port

–

No limit on the number of supported outstanding transactions

through the non-transparent bridge

–

Completely symmetric non-transparent bridge operation

allows similar/same configuration software to be run

–

Supports direct connection to a transparent or non-transparent

port of another switch

◆

Block Diagram

3-Port Switch Core

Frame Buffer

Route Table

Port

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Non-

Transparent

Bridge

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

...

SerDes

12 PCI Express Lanes

x4 Upstream Port and Two x4 Downstream Ports

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

Inc.

1 of 29

2007 Integrated Device Technology, Inc.

*Notice: The information in this document is subject to change without notice

April 11, 2007

DSC 6929

IDT 89HPES12NT3 Data Sheet

Highly Integrated Solution

–

Requires no external components

–

Incorporates on-chip internal memory for packet buffering and

queueing

–

Integrates twelve 2.5 Gbps embedded full duplex SerDes,

8B/10B encoder/decoder (no separate transceivers needed)

◆

Reliability, Availability, and Serviceability (RAS) Features

–

Upstream port can be dynamically swapped with non-trans-

parent downstream port to support failover applications

–

Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

–

Supports ECRC pass-through in transparent and non-trans-

parent ports

–

Supports Hot-Swap

◆

Power Management

–

Supports PCI Power Management Interface specification,

Revision 1.1 (PCI-PM)

–

Unused SerDes are disabled

◆

Testability and Debug Features

–

Built in SerDes Pseudo-Random Bit Stream (PRBS) generator

–

Ability to read and write any internal register via the SMBus

–

Ability to bypass link training and force any link into any mode

–

Provides statistics and performance counters

◆

Two SMBus Interfaces

–

Slave interface provides full access to all software-visible

registers by an external SMBus master

–

Master interface provides connection for an optional serial

EEPROM used for initialization

–

Master interface is also used by an external Hot-Plug I/O

expander

–

Master and slave interfaces may be tied together so the switch

can act as both master and slave

◆

Eight General Purpose Input/Output pins

◆

Packaged in 19x19mm 324-ball BGA with 1mm ball spacing

◆

management. This includes round robin port arbitration, guaranteeing

bandwidth allocation and/or latency for critical traffic classes in applica-

tions such as high throughput 10 GbE I/Os, SATA controllers, and Fibre

Channel HBAs.

Switch Configuration

The PES12NT3 is a three port switch that contains 12 PCI Express

lanes. Each of the three ports is statically allocated 4 lanes with ports

labeled as A, B and C. Port A is the upstream port, port B is the trans-

parent downstream port, and port C is the non-transparent downstream

port.

During link training, link width is automatically negotiated. Each

PES12NT3 port is capable of independently negotiating to a x4, x2 or x1

width. Thus, the PES12NT3 may be used in virtually any three port

switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.).

The PES12NT3 supports static lane reversal. For example, lane

reversal for upstream port A may be configured by asserting the PCI

Express Port A Lane Reverse (PEALREV) input signal or through serial

EEPROM or SMBus initialization. Lane reversal for ports B and C may

be enabled via a configuration space register, serial EEPROM, or the

SMBus.

Product Description

Utilizing standard PCI Express interconnect, the PES12NT3 provides

the most efficient high-performance I/O connectivity solution for applica-

tions requiring high throughput, low latency, and simple board layout

with a minimum number of board layers. With support for non-trans-

parent bridging, the PES12NT3, as a standalone switch or as a chipset

with IDT PCIe System Interconnect Switches, enables multi-host and

intelligent I/O applications requiring inter-domain communication. The

PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex

switching capacity through 12 integrated serial lanes, using proven and

robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in

both directions and is fully compliant with PCI Express Base specifica-

tion 1.0a.

The PES12NT3 is based on a flexible and efficient layered architec-

ture. The PCI Express layer consists of SerDes, Physical, Data Link and

Transaction layers in compliance with PCI Express Base specification

Revision 1.0a. The PES12NT3 can operate either as a store and

forward or cut-through switch depending on the packet size and is

designed to switch memory and I/O transactions. It supports eight Traffic

Classes (TCs) and one Virtual Channel (VC) with sophisticated resource

2 of 29

*Notice: The information in this document is subject to change without notice

April 11, 2007

IDT 89HPES12NT3 Data Sheet

CPU

PES12NT3

CPU

PES12NT3

CPU

PES12NT3

PCIe System Interconnect Switch

Embedded

CPU

Embedded

CPU

SATA / SAS

Embedded

CPU

GbE / 10GigE

Figure 2 PCIe System Interconnect Architecture Block Diagram

Controller 1

CPU

Controller 2

CPU

PES12N3

Cache Maint. &

Possible Data Flow

x4 PCIe

PES12N3

x4 PCIe

Controller

Storage

To Server

FC 2Gb/s and

4Gb/s

FC 2Gb/s and

4Gb/s

To Server

Figure 3 Dual Host Storage System

3 of 29

April 11, 2007

IDT 89HPES12NT3 Data Sheet

Pin Description

The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal

PEALREV

Type

Name/Description

PCI Express Port A Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port A are reversed. This value may be overridden by modify-

ing the value of the PALREV bit in the PA_SWCTL register.

PCI Express Port A Serial Data Receive.

Differential PCI Express receive

pairs for port A.

PCI Express Port A Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port A

PCI Express Port B Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port B are reversed. This value may be overridden by modify-

ing the value of the PBLREV bit in the PA_SWCTL register.

PCI Express Port B Serial Data Receive.

Differential PCI Express receive

pairs for port B.

PCI Express Port B Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port B

PCI Express Port C Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port C are reversed. This value may be overridden by modify-

ing the value of the PCLREV bit in the PA_SWCTL register.

PCI Express Port C Serial Data Receive.

Differential PCI Express receive

pairs for port C.

PCI Express Port C Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port C

PCI Express Reference Clock.

Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

PCI Express Reference Clock Mode Select.

These signals select the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

Table 1 PCI Express Interface Pins

PEARP[3:0]

PEARN[3:0]

PEATP[3:0]

PEATN[3:0]

PEBLREV

PEBRP[3:0]

PEBRN[3:0]

PEBTP[3:0]

PEBTN[3:0]

PECLREV

PECRP[3:0]

PECRN[3:0]

PECTP[3:0]

PECTN[3:0]

PEREFCLKP[1:0]

PEREFCLKN[1:0]

REFCLKM

Signal

MSMBADDR[4:1]

MSMBCLK

Type

I/O

Name/Description

Master SMBus Address.

These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

Master SMBus Clock.

This bidirectional signal is used to synchronize

transfers on the master SMBus. It is active and generating the clock only

when the EEPROM or I/O Expanders are being accessed.

Master SMBus Data.

This bidirectional signal is used for data on the mas-

ter SMBus.

Table 2 SMBus Interface Pins (Part 1 of 2)

MSMBDAT

I/O

4 of 29

April 11, 2007

IDT 89HPES12NT3 Data Sheet

Signal

SSMBADDR[5,3:1]

SSMBCLK

SSMBDAT

Type

I/O

Name/Description

Slave SMBus Address.

These pins determine the SMBus address to

which the slave SMBus interface responds.

Slave SMBus Clock.

This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

Slave SMBus Data.

This bidirectional signal is used for data on the slave

SMBus.

Table 2 SMBus Interface Pins (Part 2 of 2)

Signal

GPIO[0]

Type

I/O

Name/Description

General Purpose I/O.