V
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TM
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
Features
• 802.3z Gigabit Ethernet-Compliant
1.25 Gb/s Transceiver
• ANSI X3T11 Fibre Channel-Compliant
1.0625 Gb/s Transceiver
• 0.98 to 1.36 Gb/s Full-Duplex Operation
• 10-Bit TTL Interface for Transmit and
Receive Data
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
• Automatic Lock-to-Reference
• RX Cable Equalization
• Analog/Digital Signal Detection
• JTAG Access Port for Testability
• Single +3.3V Supply, 650mW Typical
• Packages: 64-Pin 10mm and 14mm PQFP and
10mm TQFP
General Description
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet Transceiver with industry-standard
pinouts. The VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK
and serializes the data onto the TX PECL differential outputs at a baud rate which is 10 times the REFCLK
frequency. Serial data input on the RX PECL differential inputs is resampled by the Clock Recovery Unit
(CRU) and deserialized onto the 10-bit receive data bus synchronously to complementary divide-by-twenty
clocks. The VSC7123 receiver detects “Comma” characters for frame alignment. An analog/digital signal
detection circuit indicates that a valid signal is present on the RX input. A cable equalizer compensates for
InterSymbol Interference (ISI) in order to increase maximum cable distances. The VSC7123 is a higher
performance, lower cost replacement for the VSC7125 and VSC7135.
VSC7123 Block Diagram
10
R(0:9)
QD
Serial to
Q Parallel D
÷10
QD
2:1
RX+
RX-
RCLK
RCLKN
COMDET
ENCDET
EWRAP
SIGDET
T(0:9)
10
Clock
Recovery
÷20
Comma
Detect
Signal
Detect
Parallel
to Serial
DQ
DQ
TX+
TX-
REFCLK
x10 Clock
Multiply
NOT SHOWN: JTAG Boundary Scan
G52212-0, Rev 4.3
03/25//01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
V
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VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
VSC7123
Functional Description
Clock Synthesizer
The VSC7123 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to
achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip Phase Lock Loop (PLL) uses a single
external 0.1
µ
F capacitor to control the Loop Filter.
Serializer
The VSC7123 accepts TTL input data as a parallel 10-bit character on the T(0:9) bus, which is latched into
the input register on the rising edge of REFCLK. This data is serialized and transmitted on the TX PECL
differential outputs at a baud rate that is 10 times the frequency of the REFCLK, with bit T0 transmitted first.
User data should be encoded using 8B/10B block code or equivalent.
Transmission Character Interface
An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the
VSC7123 corresponds to a transmission character. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping of an 8B/10B Character
Parallel Data Bits
8B/10B Bit Position
Comma Character
T9
j
X
T8
h
X
T7
g
X
T6
f
1
T5
i
1
T4
e
1
T3
d
1
T2
c
1
T1
b
0
T0
a
0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery
The VSC7123 accepts differential high-speed serial inputs on the RX+/RX- pins, extracts the clock and
retimes the data. Equalizers are included in the receiver to open the data eye and compensate for InterSymbol
Interference which may be present in the incoming data. The serial bit stream should be encoded to provide DC
balance and limited run length by an 8B/10B encoding scheme. The Clock Recovery Unit is completely
monolithic and requires no external components. For proper operation, the baud rate of the data stream to be
recovered should be within +200 ppm of 10 times the REFCLK frequency. For example, Gigabit Ethernet
systems would use 125MHz oscillators with a +100ppm accuracy resulting in +200 ppm between VSC7123
pairs.
Deserializer
The recovered serial bit stream is converted into a 10-bit parallel output character. The VSC7123 provides
complementary TTL recovered clocks, RCLK and RCLKN, which are 1/20
th
of the serial baud rate. The clocks
are generated by dividing down the high-speed recovered clock, which is phase-locked to the serial data. The
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52212-0, Rev 4.3
03/25/01
V
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LO
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TM
IT
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
serial data is retimed, deserialized and output on R(0:9). The parallel data will be captured by the adjoining
protocol logic on the rising edges of RCLK and RCLKN.
If serial input data is not present or does not meet the required baud rate, the VSC7123 will continue to
produce a recovered clock, allowing downstream logic functionality to continue. Under these circumstances,
the RCLK/RCLKN output frequency differ from its expected frequency by no more than +1%.
Word Alignment
The VSC7123 provides 7-bit comma character recognition and data word alignment. Word synchronization
is enabled by asserting ENCDET HIGH. When synchronization is enabled, the receiver examines the recovered
serial data for the presence of the “Comma” character. This pattern is “0011111XXX”, where the leading zero
corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data
character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and
K28.7, which are defined for synchronization purposes. Improper alignment of the comma character is defined
as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that R0...R6 = “0011111.”
2) The comma straddles the boundary between two 10-bit transmission characters.
3) The comma is properly aligned but occurs in the received character presented during the rising edge of
RCLK rather than RCLKN.
When ENCDET is HIGH and an improperly aligned comma is encountered, the recovered clock is
stretched (never slivered) so that the comma character and recovered clocks are properly aligned to R(0:9). This
results in proper character and word alignment. When the parallel data alignment changes in response to a
improperly aligned comma pattern, some data which would have been presented on the parallel output port may
be lost. Additionally, the first Comma pattern may also be lost or corrupted. Subsequent data will be output
correctly and properly aligned. When ENCDET is LOW, the current alignment of the serial data is maintained
indefinitely, regardless of data pattern.
When encountering a comma character, COMDET is driven HIGH. The COMDET pulse is presented
simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The
COMDET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of
RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case
when a comma character is detected and no phase adjustment is necessary. Figure 2 illustrates the position of
the COMDET pulse in relation to the comma character on R(0:9). Figure 3 shows the case where the K28.5 is
detected, but it is misaligned so a change in the output data alignment is required. Note that up to three
characters prior to the comma character may be corrupted by the realignment process.
G52212-0, Rev 4.3
03/25//01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
V
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TM
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VITESSE
SEMICONDUCTOR CORPORATION
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Figure 2: Detection of a Properly Aligned Comma Character
Data Sheet
VSC7123
RCLK
RCLKN
COMDET
R(0:9)
K28.5
TChar
TChar
TChar
TChar: 10-bit transmission character
Figure 3: Detection
Receiving Two Consecutive K28.5+TChar Transmission Words
Clock Stretching
RCLK
RCLKN
COMDET
R(0:9)
Potentially Corrupted
K28.5
TChar
TChar
TChar
K28.5
TChar
TChar: 10-bit transmission character
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52212-0, Rev 4.3
03/25/01
V
C
LO
E
Y
TM
IT
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Signal Detection
The receiver has an output, SIGDET, indicating, when HIGH, that the RX input contains a valid Fibre
Channel or Gigabit Ethernet signal. A combination of one analog and three digital checks are used to determine
if the incoming signal contains valid data. SIGDET is updated every four RCLKs. If during the current period,
all the four criteria are met, SIGDET will be HIGH during the next 4 RCLK period. If during the current period,
any of the four criteria is not met, SIGDET will be LOW during the next 4 RCLK period.
1) Analog transition detection is performed on the input to verify that the signal swings are of adequate
amplitude. The RX+/- input buffer contains a differential voltage comparator which will go HIGH if the
differential peak-to-peak amplitude is greater than 400mV or LOW if under 200mV. If the amplitude is
between 200mV and 400mV, the output is indeterminate.
2) Data on R(0:9) is monitored for all zeros (0000000000). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
3) Data on R(0:9) is monitored for all ones (1111111111). If this pattern is encountered during the current
RCLK interval, the SIGDET output will go LOW during the next four RCLK interval.
4) Data on R(0:9) is monitored for K28.5- (0011111010). Unlike previous patterns, the interval during which
a K28.5- must occur is 64K+24 10-bit characters in length. Valid Fibre Channel or Gigabit Ethernet data
will contain a K28.5- character during any period of this length. If a K28.5- is not detected during the
monitoring period, SIGDET will go LOW during the next period.
The behavior of SIGDET is affected by EWRAP and ENCDET as shown in Table 1.
Table 1: Signal Detect Behavior
EWRAP
0
0
1
1
ENCDET
0
1
0
1
COMDET
Disabled
Enabled
Disabled
Enabled
Transition
Detect
Enabled
Enabled
Enabled
Enabled
All Zeros/
All Ones
Enabled
Enabled
Disabled
Disabled
K28.5
Presence
Enabled
Disabled
Disabled
Disabled
Mode
Normal
SIGDET ignores commas
Rollback
Loopback
Note: COMDET, RCLK, RCLKN and R(0:9) are unaltered by SIGDET.
JTAG Access Port
A JTAG Access Port is provided to assist in board-level testing. Through this port, most pins can be
accessed or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this
device is available in “VSC7123/VSC7133 JTAG Access Port Functionality.”
G52212-0, Rev 4.3
03/25//01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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