VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
Features
• ANSI X3T11 Fibre Channel Compatible 1.0625
Gbps Full-duplex Transceiver
• GLM Compatible (FCSI-301-Rev 1.0)
• 20 Bit TTL Interface For Transmit And Receive Data
• Monolithic Clock Synthesis And Clock Recovery -
No External Components
• 53.125 MHz TTL Reference Clock
1.0625 Gbits/sec Fibre
Channel Transceiver
• Automatic Lock-to-Reference Function
• Suitable For Both Copper And Fiber
Optical Link Applications
• Low Power Operation - 850 mW
• 80 Pin, 14x14 mm PQFP
• Single +3.3V Power Supply
General Description
The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space- con-
strained applications. It accepts two 10-bit 8B/10B encoded transmit characters, latches them on the rising edge
of TBC and serializes the data onto the TX+/- PECL differential outputs at a baud rate which is twenty times the
TBC frequency. It also samples serial receive data on the RX+/- PECL differential inputs, recovers the clock
and data, deserializes it onto two 10-bit receive characters, outputs a recovered clocks at one twentieth of the
incoming baud rate and detects Fibre Channel “Comma” characters. The VSC7126 contains on-chip PLL cir-
cuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream.
These circuits are fully monolithic and require no external components.
VSC7126 Block Diagram
EWRAP
20
R0:19
QD
Serial to
Parallel
Retimed
Data
Recovered
Clock
QD
Clock
Recovery
2:1
RX+
RX-
RBC(0)
RBC(1)
L_UNUSE
COM_DET
EN_CDET
53.125 MHz
÷
20
Comma
Detect
Frame
Logic
20
T0:19
DQ
Parallel
to Serial
Serial Data
Synthesized
Clock
DQ
TX+
TX-
53.125 MHz
TBC
TXEN#
PLL Clock
Multiply (x20)
G52148-0, Rev. 4.3
3/4/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Datasheet
VSC7126
Functional Description
Clock Synthesizer:
The VSC7126 clock synthesizer multiplies the 53.125 MHz reference frequency provided on the TBC pin
by 20 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic
PLL which does not require any external components.
Serializer:
The VSC7126 accepts TTL input data as two parallel 10 bit characters on the T0:19 bus which is latched
into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL dif-
ferential outputs at a baud rate of twenty times the frequency of the TBC input, with bit T0 transmitted first.
User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel spec-
ification, or an equivalent, edge rich, DC-balanced code. If either EWRAP or TXEN# is HIGH the transmitter
will be disabled with TX+ HIGH and TX- LOW. If both EWRAP and TXEN# are LOW, the transmitter outputs
serialized data.
Transmission Character Interface
In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20 bit inter-
face on the VSC7126 corresponds to two transmission characters. This mapping is illustrated in Figure 1.
Figure 1: Transmission Order and Mapping to Fibre Channel Character
Parallel Data Bits
8B/10B Bit Position
Valid Comma Position
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
j
h
g
f
i
e
d
c
b
a
j
h
g
f
1
i
1
e
1
d
1
c
1
b
0
a
0
Last Data Bit Transmitted
First Data Bit Transmitted
Clock Recovery:
The VSC7126 accepts differential high speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW),
extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and lim-
ited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7126 clock recovery
circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of
the data stream to be recovered should be within 200 ppm of twenty times the TBC frequency. This allows
oscillators on either end of the link to be 53.125 MHz +/- 100ppm.
Deserializer:
The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7126 provides
a TTL recovered clock, RBC(0) and its complement RBC(1), at one-twentieth of the serial baud rate. The
clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial
data is retimed by the internal high-speed clock, and deserialized. The resulting parallel data will be captured
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52148-0, Rev. 4.3
3/4/99
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
1.0625 Gbits/sec Fibre
Channel Transceiver
by the adjoining protocol logic on the falling edge of RBC(0). In order to maximize the setup and hold times
available at this interface, the parallel data is loaded into the output register at a point nominally midway
between the falling edges of RBC(0).
If serial input data is not present, or does not meet the required baud rate, the VSC7126 will continue to
produce a recovered clock so that downstream logic may continue to function. In the absence of a signal, the
RBC(0)/RBC(1) output clocks will immediately lock to the TBC reference clock.
Word Alignment:
The VSC7126 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word
synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7126
constantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is
“0011111XXX”, where the leading zero corresponds to the first bit received. The comma sequence is not con-
tained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special
characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in Fibre
Channel systems. Improper alignment of the comma character is defined as any of the following conditions:
1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = “0011111”
2) The comma straddles the boundary between two 10-bit transmission characters.
When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in
such a manner that the comma character is aligned properly in R0:6 as shown in Figure 1. This results in proper
character and word alignment. When the parallel data alignment changes in response to an improperly aligned
comma pattern, some data which would have been presented on the parallel output port may be lost. However,
the synchronization character and subsequent data will be output correctly and properly aligned. When
EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.
On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the
parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma char-
acter and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the
adjoining protocol logic on the falling edge of RBC(0). Functional waveforms for synchronization are given in
Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is
necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:6.
Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in the output data align-
ment is required. Note that up to three characters prior to the comma character may be corrupted by the realign-
ment process.
Signal Detection:
An output, LUNUSE, is provided to signal when the link is open or down. This signal is asserted if R0:19
are all either LOW or HIGH and EWRAP is LOW.
G52148-0, Rev. 4.3
3/4/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Figure 2: Detection of a Properly Aligned Comma Character
Datasheet
VSC7126
RBC(0)
COM_DET
R0:9
R10:19
K28.5
TChar
TChar
TChar
TChar
TChar
TChar
TChar
TChar: 10 bit Transmission Character
Figure 3: Detection and Resynchronization of an Improperly Aligned Comma
Receiving Two Consecutive K28.5+TChar Transmission Words
RBC(0)
COM_DET
R0:9
R10:19
PC
PC
PC
K28.5
TChar
TChar
TChar
TChar
TChar
TChar
TChar
K28.5
TChar
TChar
TChar
PC = Potentially Corrupted
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52148-0, Rev. 4.3
3/4/99
VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC7126
AC Characteristics
Figure 4: Transmit Timing Waveforms
1.0625 Gbits/sec Fibre
Channel Transceiver
TBC
T
1
T
2
T0:19
20 Bit Data
Data Valid
Data Valid
Data Valid
Table 1: Transmit AC Characteristics
Parameters
T
1
T
2
T
SDR
,T
SDF
T
LAT
Description
T0:19 Setup time to the
rising edge of TBC
T0:19 hold time after the
rising edge of TBC
TX+/TX- rise and fall time
Latency from rising edge
of TBC to T0 appearing on
TX+/TX-
Serial data output random
jitter (RMS)
Serial data output
deterministic jitter (p-p)
Min
1.5
2.5
—
20 bc - 4 ns
Max
—
—
300
Units
ns.
ns.
ps.
ns.
Conditions
Measured between the valid data level of
T0:19 to the 1.4V point of TBC
20% to 80%, 75 Ohm load to Vdd-2V
Tested on a sample basis
bc = Bit Clock Periods
Transmitter Output Jitter Allocation
T
RJ
T
DJ
—
—
20
120
ps.
ps.
RMS, tested on a sample basis
(refer to Figure 8)
Peak to peak, tested on a sample basis
(refer to Figure 8)
G52148-0, Rev. 4.3
3/4/99
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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