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5962F9672501VRC

产品描述ACT SERIES, POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20
产品类别逻辑    逻辑   
文件大小44KB,共3页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
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5962F9672501VRC概述

ACT SERIES, POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20

5962F9672501VRC规格参数

参数名称属性值
零件包装代码DIP
包装说明DIP,
针数20
Reach Compliance Codeunknown
系列ACT
JESD-30 代码R-CDIP-T20
JESD-609代码e4
逻辑集成电路类型D LATCH
位数8
功能数量1
端子数量20
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
传播延迟(tpd)18 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量300k Rad(Si) V
触发器类型POSITIVE EDGE
宽度7.62 mm
Base Number Matches1

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ACTS573MS
January 1996
Radiation Hardened Octal
Three-State Transparent Latch
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96725 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 18ns (Max), 12ns (Typ)
GND 10
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
Description
The Intersil ACTS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACTS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line package (D suffix).
D7
GND
Ordering Information
PART NUMBER
5962F9672501VRC
5962F9672501VXC
ACTS573D/Sample
ACTS573K/Sample
ACTS573HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
1
518892
File Number
4092

5962F9672501VRC相似产品对比

5962F9672501VRC 5962F9672501VXC
描述 ACT SERIES, POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20 ACT SERIES, POSITIVE EDGE TRIGGERED D LATCH, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
零件包装代码 DIP DFP
包装说明 DIP, DFP,
针数 20 20
Reach Compliance Code unknown unknown
系列 ACT ACT
JESD-30 代码 R-CDIP-T20 R-CDFP-F20
JESD-609代码 e4 e4
逻辑集成电路类型 D LATCH D LATCH
位数 8 8
功能数量 1 1
端子数量 20 20
最高工作温度 125 °C 125 °C
最低工作温度 -55 °C -55 °C
输出特性 3-STATE 3-STATE
输出极性 TRUE TRUE
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DFP
封装形状 RECTANGULAR RECTANGULAR
封装形式 IN-LINE FLATPACK
传播延迟(tpd) 18 ns 18 ns
认证状态 Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V
座面最大高度 5.08 mm 2.92 mm
最大供电电压 (Vsup) 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V
表面贴装 NO YES
技术 CMOS CMOS
温度等级 MILITARY MILITARY
端子面层 GOLD GOLD
端子形式 THROUGH-HOLE FLAT
端子节距 2.54 mm 1.27 mm
端子位置 DUAL DUAL
总剂量 300k Rad(Si) V 300k Rad(Si) V
触发器类型 POSITIVE EDGE POSITIVE EDGE
宽度 7.62 mm 6.92 mm
Base Number Matches 1 1

 
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