1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT8JSF12864H – 1GB
MT8JSF25664H – 2GB
Features
•
DDR3 functionality and operations supported as de-
fined in the component data sheet
•
204-pin, small-outline dual in-line memory module
(SODIMM)
•
Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
•
1GB (128 Meg x 64) and 2GB (256 Meg x 64)
•
Vdd = 1.5V ±0.075V
•
Vddspd = +3.0V to +3.6V
•
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
•
Single rank
•
On-board I
2
C temperature sensor with integrated se-
rial presence-detect (SPD) EEPROM
•
8 internal device banks
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
•
Selectable BC4 or BL8 on-the-fly (OTF)
•
Gold edge contacts
•
Lead-free
•
Fly-by topology
•
Terminated control, command, and address bus
Table 1: Key Timing Parameters
Speed
Grade
-1G6
-1G4
-1G1
-1G0
-80C
-80B
Industry
Nomenclature
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 11 CL = 10
1600
–
–
–
–
–
1333
1333
–
–
–
–
CL = 9
1333
1333
–
–
–
–
CL = 8
1066
1066
1066
1066
–
–
CL = 7
1066
1066
1066
–
–
–
CL = 6
800
800
800
800
800
800
CL = 5
667
667
667
667
800
667
t
RCD
t
RP
t
RC
Figure 1: 204-Pin SODIMM (MO-268 R/C B)
Module height: 30.0mm (1.18in)
Options
•
Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
•
Package
–
204-pin lead-free DIMM
•
Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
Notes:
Marking
None
I
Y
-1G6
-1G4
-1G1
1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
(ns)
13.125
13.125
13.125
15
12.5
15
(ns)
13.125
13.125
13.125
15
12.5
15
(ns)
48.125
49.125
50.625
52.5
50
52.5
PDF: 09005aef82b36df5
Rev. C 8/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007
Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
1GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
2GB
8K
32K A[14:0]
8 BA[2:0]
2Gb (256 Meg x 8)
1K A[9:0]
1 S0#
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Part
Number
2
Module Density
1GB
1GB
1GB
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
MT8JSF12864H(I)Y-1G6__
MT8JSF12864H(I)Y-1G4__
MT8JSF12864H(I)Y-1G1__
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Part
Number
2
Module Density
2GB
2GB
2GB
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
MT8JSF25664H(I)Y-1G6__
MT8JSF25664H(I)Y-1G4__
MT8JSF25664H(I)Y-1G1__
Notes:
1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-
sult factory for current revision codes. Example: MT8JSF12864HY-1G1B1.
PDF: 09005aef82b36df5
Rev. C 8/09 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007
Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assigments and Descriptions
Pin Assigments and Descriptions
Table 5: Pin Assignments
204-Pin DDR3 SODIMM Front
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Symbol
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
Pin
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
Symbol
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0#
Pin
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
Symbol
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
A13
NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
Pin
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
–
–
Symbol
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
–
–
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Symbol
V
SS
DQ4
DQ5
V
SS
DQS0#
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
RESET#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
204-Pin DDR3 SODIMM Back
Pin
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
Symbol
V
SS
DQ28
DQ29
V
SS
DQ3#
DQ3
V
SS
DQ30
DQ31
V
SS
NC
V
DD
NC
NF/A14
1
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
CK1
CK1#
Pin
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
Symbol
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
NC
NC
V
DD
V
REFCA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
Pin
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
–
–
Symbol
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
EVENT#
SDA
SCL
V
TT
–
–
Note:
1. Pin 80 is NF for 1GB and A14 for 2GB.
PDF: 09005aef82b36df5
Rev. C 8/09 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007
Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assigments and Descriptions
Table 6: Pin Descriptions
Symbol
A[14:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 is sampled during a PRECHARGE com-
mand to determine whether the PRECHARGE applies to one bank (A10 LOW, bank selec-
ted by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS
commands. The address inputs also provide the op-code during the mode register com-
mand set. A[13:0] address the 1Gb DDR3 devices. A[14:0] address the 2Gb DDR3 devices.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DRAM. When enabled in normal operation, ODT is only
applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if
disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being en-
tered.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver is
a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
and DC LOW
≤
0.2 ×
V
DD
. RESET# assertion and deassertion are asynchronous. System applications will most like-
ly be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate
receiver design is recommended along with implementing on-chip noise filtering to pre-
vent false triggering (RESET# assertion minimum pulse width is 100ns).
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command de-
coder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD EE-
PROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
BA[2:0]
Input
CK0, CK0#
CKE0
DM[7:0]
Input
Input
Input
ODT0
Input
RAS#, CAS#,
WE#
RESET#
Input
Input
(LVCMOS)
S0#
SA[1:0]
SCL
DQ[63:0]
DQS[7:0]
DQS#[7:0]
SDA
Input
Input
Input
I/O
I/O
I/O
PDF: 09005aef82b36df5
Rev. C 8/09 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007
Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assigments and Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
EVENT#
V
DD
V
DDSPD
V
REFCA
V
REFDQ
V
SS
V
TT
NC
NF
Type
Description
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
Supply
Supply
Supply
Supply
Supply
Supply
–
–
Power supply:
1.5V ±0.075V. The component V
DD
and V
DDQ
are connected to the module
V
DD
.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
Control, command, and address (V
DD
/2).
Reference voltage:
DQ, DM (V
DD
/2).
Ground.
Termination voltage:
Used for control, command, and address (V
DD
/2).
No connect:
These pins are not connected on the module.
No function:
Connected within the module, but provides no functionality.
PDF: 09005aef82b36df5
Rev. C 8/09 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2007
Micron Technology, Inc. All rights reserved.
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