— Supports control, interrupt, bulk transfers for all
endpoints
— Supports isochronous transfers for 4 endpoints
— 5 V tolerant I/O buffers allow operation in 3.3 V
or 5 V environments
Integrated ARM7TDMS core operating at up to
80 MHz
4K x 32 on-chip ROM
2K x 32 on-chip RAM
On-chip PLL generates high-speed clocks from 30
MHz external source.
Requires single 3.3 V external supply (1.5 V. on-
chip regulator supplies internal core).
Provides 16-bit external memory interface (EMI)
I
2
C interface for non-volatile configuration
24 general purpose I/O (GPIO) pins
Two programmable 32-bit timers.
Reset/clock/power management.
Programmable interrupt controller (PIC) to priori-
tize and mask interrupts.
Supports
IEEE
1149.1 JTAG.
Programmable eight-channel DMA controller.
128-pin TQFP package (lead-free), 14 mm x 22
mm, 0.5 mm pitch, 0.14 µm process
Introduction
The USS2828 is a general purpose USB 2.0 device
controller that supports both high-speed (480 Mbits/
s) and full-speed (12 Mbits/s) data transfers and can
be used in a variety of USB applications such as
printers, cameras, scanners and adapters. The
device includes an integrated ARM7TDMS processor
core with on-chip ROM and RAM, a 24-bit GPIO
interface and provides an external memory interface
(EMI) to support memory-mapped devices.
USS2828
USB 2.0 High Speed Device Controller
Product Brief
April 2005
Functional Description
TCK
TDI
TMS
TDO
TRSTB
ARM7TDMS
JTAG
AHB
BUS
ROM
4K x 32
DMA
CONTROLLER
USB 2.0
DEVICE
CONTROLLER
USB 2.0 PHY
RAM
2K
x 32
MEMORY
CONTROLLER
(EMI)
ADDR
DATA
RD_N
WR_N
CS1_N
CS2_N
ROM_CS_N
RAM_CS_N
IRQ1_N
IRQ2_N
30 MHz USB CLOCK
D+, D–
RREF
GPIO[23:0]
GPIO
PROGRAMMABLE
INTERRUPT
CONTROLLER
AHB — APB
BRIDGE
CLOCK/RESET
POWER
MANAGMENT
APB
BUS
I
2
C INTERFACE
EEPROM
SDA
SCK
RESET_N
SYSTEM CLOCK (TO 80 MHz)
PLL OUTPUT (TO 480 MHz)
Figure 1. USS2828 Block Diagram
ARM Core and AMBA AHB/APB Bus
The USS2828 device is based on an ARM7TDMS
core. The ARM7TDMS core runs at clock speeds of up
to 80 MHz providing 40 MIPS of performance. A JTAG
interface is provided for connecting to the ARM devel-
opment tools. On-chip memories, 4K x 32 ROM and
2K x 32 RAM, are accessible with zero wait states.
USB2.0 Controller
The USB 2.0 controller includes USB 2.0 full-speed
and high-speed USB transceivers for data transfers
using a maximum of 16 bidirectional endpoints (8 IN
endpoints and 8 OUT endpoints). It can be used in both
bus-powered and self-powered modes. Transfers over
the USB bus are controlled by an external 30 MHz
crystal. A 2 Kbyte FIFO is shared between the enabled
endpoints to transfer data over the internal AHB bus
running at 80 MHz.
2
Agere Systems Inc.
Product Brief
April 2005
External Memory Interface (EMI)
The USS2828 contains a memory controller to inter-
face with external Flash ROM, RAM, or other memory
devices and allows use of mixed on-chip and external
memories. The EMI provides four chip selects and a
16-bit data bus with 24 address lines and supports both
8-bit and 16-bit memories with programmable wait
states for read/write accesses.
USS2828
USB 2.0 High Speed Device Controller
General Purpose I/O (GPIO)
The GPIO module is an AHB slave that provides
24 bits of programmable general-purpose inputs/out-
puts.
All GPIO pins are 5 V tolerant to allow operation in both
3.3 V and 5 V environments. A data direction register is
used to control the direction (input or output) of the
associated GPIO pin, and each pin, as well as its inter-
nal pull-up, can be enabled/disabled via a register
write.
I
2
C Interface
The EEPROM interface is a two-wire, bidirectional I
2
C
bus compliant with version 2.1 of the I
2
C specification.
Typically in USB applications, the serial EEPROM is
used to store small amounts of configuration informa-
tion such as IDs, serial numbers, etc.
I
2
C features supported in this design include the follow-
ing:
Two data rates: 100 Kbits/s and 400 Kbits/s.
Single master operation supporting multiple slave
devices.
Programmable normal or extended addressing (7-bit
or 10-bit).
Transfer status interrupts and flags.
Voltage Regulators
The USS2828 has an internal voltage regulator that will
provide 1.5 V from the 3.3 V external voltage supply.
For 1.5 V operation, the ext15 pin is used to control the
switching between the external and internal voltage
regulators. If the external voltage must be used, then
this pin must be pulled high.
On-chip test and debug features
There are five hardware test modes on USS2828 con-
trolled by three test_sel pins. The test modes use
JTAG, DAA, GPI/O, and EMI interfaces to connect to
internal test hardware. In addition to this, a dedicated
observe pin controls the test mode which allows moni-
toring all UTMI internal interface signals on external
EMI interface.
A standard 5-wire JTAG interface is available to load
and debug software using ARM development tools.
This interface can also be used for loading production
tests.
Clock and Power Control
An on-chip, powerup reset generator works in conjunc-
tion with an external RESET signal to control the inter-
nal reset of the device. The external 30 MHz crystal
and internal PLL's 480 MHz output provide the clock
sources to the device. At powerup, the crystal interface
is enabled and the PLL output is not used. The ARM7
core runs at the 30 MHz crystal rate and boots from on-
chip ROM. The ARM7 clock can be programmed up to
80 MHz by switching to the PLL output in conjunction
with clock divider setting under software control.
There are independent clocks for most peripherals on
the USS2828, allowing blocks not required in any spe-
cific mode to be disabled in order to minimize power
dissipation.
Agere Systems Inc.
3
USS2828
USB 2.0 High Speed Device Controller
Product Brief
April 2005
Ordering Information
Table 1. Chip Set Names and Part Numbers
Device
USS2828
Package
128-pin TQFP
Part Number
L-USS2828-T128A-DB
L-USS2828-T128A-DT
Comcode
700 074 087
700 074 088
Description
Dry Baked Tray
Dry Baked Reel
For additional information, contact your Agere Systems Account Manager or the following:
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1-800-372-2447,
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(Taipei)
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Tel. (44) 1344 296 400
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