3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
128 x 128
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
IDT72V8988
128 x 128 channel non-blocking switch
Automatic signal identification (ST-BUS
®
, GCI)
4 RX inputs—32 channels at 64 Kbit/s per serial line
4 TX outputs—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
3.3V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and
44-pin Plastic Quad Flatpack (PQFP)
°
°
Operating Temperature Range -40°C to +85°C
3.3V I/O with 5V Tolerant Inputs
per-channel variable or constant throughput delay modes and microprocessor
read and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8988 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
Frame sequence, constant throughput delay, and guaranteed minimum
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT72V8988 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the four serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
In Processor Mode, the microprocessor can access the input and output time
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS
®
formats, IDT72V8988 has incorporated an
internal circuit to automatically identify the polarity and format of the frame
synchronization.
A functional block diagram of the IDT72V8988 device is shown on page 1.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and
DESCRIPTION:
The IDT72V8988 is an ST-BUS
®
/GCI compatible digital switch controlled
by a microprocessor. The IDT72V8988 can handle as many as 128, 64 Kbit/s
input and output channels. Those 128 channels are divided into 4 serial inputs
and outputs, each of which consists of 32 channels. The IDT72V8988 provides
FUNCTIONAL BLOCK DIAGRAM
C4i
F0i
V
CC
GND
ODE
Timing
Unit
RX0
RX1
RX2
RX3
Output MUX
TX0
Receive
Serial Data
Streams
Data
Memory
Control Register
Connection
Memory
Transmit
Serial Data
Streams
TX1
TX2
TX3
Microprocessor Interface
5704 drw01
DS
CS
R/W A0/
DTA
D0/
A5
D7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
is a trademark of Mitel Corp.
AUGUST 2003
DSC-5704/5
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
PIN CONFIGURATION
DNC
(1)
DNC
(1)
DTA
INDEX
6
5
4
3
2
44
43
42
41
RX3
V
CC
V
CC
V
CC
V
CC
V
CC
F0i
C4i
A
0
A
1
A
2
1
40
DNC
(1)
RX2
RX1
RX0
ODE
TX0
TX1
TX2
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TX3
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
GND
D
0
D
1
D
2
D
3
D
4
18
19
20
21
22
23
24
25
26
27
A
3
A
4
A
5
D
7
D
6
DNC
(1)
D
5
DNC
(1)
33
32
31
30
29
28
27
26
25
24
23
DS
R/
W
CS
28
5704 drw02
PLCC: 0.05in. pitch, 0.65in. x 0.65in
(J44-1, order code: J)
TOP VIEW
DTA
DNC
(1)
DNC
(1)
INDEX
44
43
42
41
40
39
38
37
36
35
RX3
V
CC
V
CC
V
CC
V
CC
V
CC
F0i
C4i
A
0
A
1
A
2
34
DNC
(1)
ODE
TX0
RX2
RX1
RX0
TX1
TX2
1
2
3
4
5
6
7
8
9
10
11
TX3
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
GND
D
0
D
1
D
2
D
3
D
4
12
13
14
15
16
17
18
19
20
21
22
5704 drw03
A
3
A
4
A
5
CS
D
7
D
6
DNC
(1)
D
5
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
NOTES:
1. DNC - Do Not Connect.
2
DNC
(1)
DS
R/
W
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
PIN DESCRIPTIONS
SYMBOL
GND
V
CC
NAME
Ground.
V
CC
Data Acknowledgment
(Open Drain)
RX Input 0 to 3
Frame Pulse
Clock
Address 0 to 5
Data Strobe
Read/Write
Chip Select
Data Bus 0 to 7
TX Outputs 0 to 3
(Three-state Outputs)
Output Drive Enable
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input accepts and automatically identifies frame synchronization signals formatted according to different
backplane specifications such as ST-BUS
®
and
GCI.
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT72V8988 internal registers.
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS
to enable the internal read and write generation.
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
DTA
RX0-3
O
I
I
I
I
I
I
I
I/O
O
I
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-3
ODE
3
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
FUNCTIONAL DESCRIPTION (Cont'd)
four output (TX0-3) serial streams are provided in the IDT72V8988 device
allowing a complete 128 x 128 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 128-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i,
the incoming serial data streams can be framed and sequentially addressed.
Depending on the type of information to be switched, the IDT72V8988 device
can be programmed to perform time slot interchange functions with different
throughput delay capabilities on a per-channel basis. The Variable Delay
mode, most commonly used for voice applications, can be selected ensuring
minimum throughput delay between input and output data. In Constant Delay
mode, used in multiple or grouped channel data applications, the integrity of the
information through the switch is maintained.
CONNECTION MEMORY
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is split into HIGH
and LOW parts and is associated with particular TX output streams. In Processor
Mode, data output on the TX streams is taken from the Connection Memory Low
and originates from the microprocessor (Figure 2). Where as in Connection
Mode (Figure 1), data is read from Data Memory and originated from the
incoming RX streams. Data destined for a particular channel on the serial output
stream is read internally during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters before being output. By having the output channel to specify
the input channel through the Connection Memory, the same input channel can
be broadcast to several output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locations which correspond to the output link and channel number. The contents
of the Connection Memory Low are transferred to the parallel-to-serial
converter one channel before it is to be output and are transmitted each frame
to the output until it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT72V8988. Output channels are selected into
specific modes such as: Processor Mode or Connection mode, Variable or
Constant throughput delay modes, Output Drivers Enabled or in three-state
condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master output three-state control pin. If the ODE input
is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high
impedance regardless Connection Memory High programming. However, if
ODE is HIGH, the contents of Connection Memory High control the output state
on a per-channel basis.
SERIAL INTERFACE TIMING
The IDT72V8988 master clock (C4i) is 4.096 MHz signal allowing serial data
link configuration at 2.048 Mb/s to be implemented. The IDT72V8988 can
automatically detect the presence of an input frame pulse, identify the type of
backplane present on the serial interface, and format the synchronization pulse
according to ST-BUS
®
or GCI interface specifications (active HIGH in GCI or
active LOW in ST-BUS
®
). Upon determining the correct interface Connected
to the serial port, the internal timing unit establishes the appropriate serial data
bit transmit and sampling edges. In ST-BUS
®
mode, every second falling edge
of the 4.096 MHz clock marks a boundary and the input data is clocked in by
the rising edge, three quarters of the way into the bit cell. In GCI mode every
second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit
boundaries.
DELAY THROUGH THE IDT72V8988
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the
IDT72V8988 device varies according to the mode selected in the
V/C
bit of the
Connection Memory High.
VARIABLE DELAY MODE
The delay in Variable Delay Mode is dependent only on the combination
of source and destination on the input and output streams. The minimum delay
achievable in the IDT72V8988 device is three time slots. In the IDT72V8988
device, the information that is to be output in the same channel position as the
information is input (position n), relative to frame pulse, will be output in the
following frame (channel n, frame n+1). The same occurs if the input channels
succeeding (n+1, n+2) the channel position as the information is input.
RX
Receive
Serial Data
Streams
Data
Memory
Connection
Memory
Transmit
Serial Data
Streams
TX
Receive
Serial Data
Streams
Data
Memory
Connection
Memory
Transmit
Serial Data
Streams
TX
5704 drw06
5704 drw05
Microprocessor
Figure 1. Connection Mode
4
Figure 2. Processor Mode
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
Commercial Temperature Range
The information switched to the third time slot after the input has entered the
device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), will always appear on the output three channels later in the
same incoming frame.
Any switching configuration that provides three or more time slots between
input and output channels, will have a throughput delay equal to the difference
between the output and input channels; i.e., the throughput delay will be less
than one frame. Table 1 shows the possible delays for the IDT72V8988 device
in Variable Delay Mode. An example is shown in Figure 3.
CONSTANT DELAY MODE
In this mode frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8988, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
To summarize, any input time slot from input frame N will be always switched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
SOFTWARE CONTROL
If the A5, A1, A0 address line inputs are LOW then the IDT72V8988 Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8988 Data and
Connect memories. See Figure 6 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
Stream Address bits define internal memory subsections corresponding to input
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, Table 5) are output on the output streams once every frame unless
the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8988 behaves as
if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory
High (CMH, Table 4) locations were set to HIGH, regardless of the actual value.
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) for that particular channel.
INITIALIZATION
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two Connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
As the connection memory can be in any state after a power up, the ODE
pin should be used to hold the TX streams in high-impedance until the per-
channel output enable control in the connection memory high is appropriately
programmed.
MICROPROCESSOR PORT
The IDT72V8988 microprocessor port is a non-multiplexed bus architec-
ture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address
input lines (A0-A5) and four control lines (CS, DS, R/W and
DTA).
This parallel
microport allows the access to the Control Registers, Connection Memory Low,
Connection Memory High, and the Data Memory. All locations are read/write
access able except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (DTA). In the IDT72V8988
device, the
DTA
output provides a maximum acknowledgment delay of 800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
TABLE 1
VARIABLE DELAY MODE
Input Channel
n
n
n
Output Channel
m=n, n+1 or n+2
m>n+2
m<n
Throughput Delay
m-n+32 time slot
m-n time slot
32-(n-m) time slot
TABLE 2
ADDRESS MAPPING
A5
0
1
1
1
1
1
1
1
1
5
A4
X
0
0
•
•
•
•
•
A3
X
0
0
•
•
•
•
•
A2
X
0
0
•
•
•
•
•
A1
0
0
0
•
•
•
•
•
A0
0
0
1
•
•
•
•
•
LOCATION
Control Register
Channel 0
Channel 1
•
•
•
•
•
1
1
1
1
1
Channel 31
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
