April 2008
IDSH51–02A1F1C
IDSH51–03A1F1C
IDSH51–04A1F1C
512-Mbit Double-Data-Rate-Three SDRAM
DDR3 SDRAM
RoHS Compliant Products
Advance
Internet Data Sheet
Rev. 0.92
Advance Internet Data Sheet
IDSH51–0[2/3/4]A1F1C
512-Mbit Double-Data-Rate-Three SDRAM
Revision History: Rev. 0.92, 2008-04
Overview major changes since last revision
Adapted internet edition
All
Editorial Changes
Added new figure mpth0535
Added new column “EDA Signal Name“ in table 3
Added new notes after table “Clock to Data Strobe Relationship”
Changed the footnote 12 in table 65, Maximum external load capacitance on ZQ signal: 5 pF
Changed text in chapter “ZQ Calibration Commands”
Added new figure “Definition of Output Crosspoint Voltage for DQS and DQS”
Changed text for Vox in table “AC Output Levels for Differential Signals”
Added more text to table :”Cross Point Voltage for Differential Input Signals “
new text for Single-Ended Requirements for Differential Signals
Corrected Table 42 according industry standard letter ballot
In Tabelle 41 "DC and AC Input Levels for Single-Ended Signals" :
- VIH.DC set to VDD
- VIL.DC set to VSS
29
5
Corrected CWL in table 11, MR2 Mode register Definition (BA[2:0]=010B)
Updated the ordering information, added Supported CAS latencies
Previous Revision: Rev. 0.91, 2007-09
Previous Revision: Rev. 0.90, 2007-05
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
02092007-PWZB-VR0U
2
Advance Internet Data Sheet
IDSH51–0[2/3/4]A1F1C
512-Mbit Double-Data-Rate-Three SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Three (DDR3) SDRAM component product family and
describes its main characteristics.
1.1
Features
• Burst length 8 (BL8) and burst chop 4(BC4) modes: fixed
via mode register (MRS) or selectable On-The-Fly (OTF)
• Programmable read burst ordering: interleaved or nibble
sequential
• Multi-purpose register (MPR) for readout of non-memory
related information
• System level timing calibration support via write leveling
and MPR read pattern
• Differential clock inputs (CK/CK)
• Bi-directional, differential data strobe pair (DQS/DQS) is
transmitted / received with data. Edge aligned with read
data and center-aligned with write data
• DLL aligns transmitted read data and strobe pair transition
with clock
• Push-pull output driver with nominal
R
ON
of 34
Ω
at
V
OUT
=
V
DDQ
/2
• Programmable on-die termination (ODT) for data, data
mask and differential strobe pairs
• Dynamic ODT mode for improved signal integrity and pre-
selectable termination impedances during writes
• ZQ Calibration for output driver and on-die termination
using external reference resistor to ground
• Two reference voltage inputs
V
REFDQ
,
V
REFCA
• Lead and halogen free packages: 78 ball (PG-TFBGA-78)
for
×4
and
×8
components; 96 ball (PG-TFBGA-96) for
×16
components, 0.8
×
0.8 mm ball pitch
The 512Mbit DDR3 SDRAM offers the following key features:
• 1.5 V ± 0.075 V supply voltage for
V
DD
and
V
DDQ
• SDRAM configurations with
×4, ×8
and
×16
data in/outputs
• Eight internal banks for concurrent operation
• 8-Bit prefetch architecture
• Page Size:1 kByte page size for
×4
and
×8;
2 kByte page
size for
×16
components
• Asynchronous RESET
• Auto-Precharge operation for read and write commands
• Refresh, Self-Refresh and power saving Power-down
modes; Auto Self-refresh (ASR) and Partial array self
refresh (PASR)
• Average Refresh Period 7.8 µs at a
T
OPER
up to 85 °C,
3.9 µs up to 95 °C
• Operating temperature range 0 - 85 °C and 85 - 95 °C
• Data mask function for write operation
• Commands can be entered on each positive clock edge
• Data and data mask are referenced to both edges of a
differential data strobe pair (double data rate)
• CAS latency (CL): 5, 6, 7, 8, 9 and 10
• Posted CAS with programmable additive latency (AL = 0,
CL–1 and CL–2) for improved command, address and
data bus efficiency
• Read Latency RL = AL + CL
• Programmable CAS Write Latency (CWL) per operating
frequency
• Write Latency WL = AL + CWL
Rev. 0.92, 2008-04
02092007-PWZB-VR0U
3
Advance Internet Data Sheet
IDSH51–0[2/3/4]A1F1C
512-Mbit Double-Data-Rate-Three SDRAM
1.2
Product List
Table 1
shows all possible products within the 512 Mbit DDR3 SDRAM first component generation. Availability depends on
application needs. For Qimonda part number nomenclature see
Chapter 6.
TABLE 1
Ordering Information for 512 Mbit DDR3 Components
QAG Part Number
Max. Clock
frequency
400 MHz
400 MHz
533 MHz
533 MHz
533 MHz
667 MHz
667 MHz
667 MHz
800 MHz
800 MHz
400 MHz
400 MHz
533 MHz
533 MHz
533 MHz
667 MHz
667 MHz
667 MHz
800 MHz
800 MHz
400 MHz
400 MHz
533 MHz
533 MHz
533 MHz
667 MHz
667 MHz
667 MHz
800 MHz
800 MHz
CAS-RCD-RP
latencies
5–5–5
6–6–6
6–6–6
7–7–7
8–8–8
8–8–8
9–9–9
10–10–10
9–9–9
10–10–10
5–5–5
6–6–6
6–6–6
7–7–7
8–8–8
8–8–8
9–9–9
10–10–10
9–9–9
10–10–10
5–5–5
6–6–6
6–6–6
7–7–7
8–8–8
8–8–8
9–9–9
10–10–10
9–9–9
10–10–10
Supported CAS
latencies
5, 6
6
5, 6, 7, 8
6, 7, 8
6, 8
5, 6, 7, 8, 9, 10
6, 8, 9, 10
6, 8,10
5, 6, 7, 8, 9, 10
5, 6, 7, 8, 9, 10
5, 6
6
5, 6, 7, 8
6, 7, 8
6, 8
5, 6, 7, 8, 9, 10
6, 8, 9, 10
6, 8,10
5, 6, 7, 8, 9, 10
5, 6, 7, 8, 9, 10
5, 6
6
5, 6, 7, 8
6, 7, 8
6, 8
5, 6, 7, 8, 9, 10
6, 8, 9, 10
6, 8,10
5, 6, 7, 8, 9, 10
5, 6, 7, 8, 9, 10
Speed Sort
Name
DDR3–800D
DDR3–800E
DDR3–1066E
DDR3–1066F
DDR3–1066G
DDR3–1333G
DDR3–1333H
DDR3–1333J
DDR3–1600H
DDR3–1600J
DDR3–800D
DDR3–800E
DDR3–1066E
DDR3–1066F
DDR3–1066G
DDR3–1333G
DDR3–1333H
DDR3–1333J
DDR3–1600H
DDR3–1600J
DDR3–800D
DDR3–800E
DDR3–1066E
DDR3–1066F
DDR3–1066G
DDR3–1333G
DDR3–1333H
DDR3–1333J
DDR3–1600H
DDR3–1600J
Package
512 Mbit DDR3 SDRAM Components in
×
4 Organization (128 Mbit
×
4)
IDSH51–02A1F1C–08D
IDSH51–02A1F1C–08E
IDSH51–02A1F1C–10E
IDSH51–02A1F1C–10F
IDSH51–02A1F1C–10G
IDSH51–02A1F1C–13G
IDSH51–02A1F1C–13H
IDSH51–02A1F1C–13J
IDSH51–02A1F1C–16H
IDSH51–02A1F1C–16J
IDSH51–03A1F1C–08D
IDSH51–03A1F1C–08E
IDSH51–03A1F1C–10E
IDSH51–03A1F1C–10F
IDSH51–03A1F1C–10G
IDSH51–03A1F1C–13G
IDSH51–03A1F1C–13H
IDSH51–03A1F1C–13J
IDSH51–03A1F1C–16H
IDSH51–03A1F1C–16J
IDSH51–04A1F1C–08D
IDSH51–04A1F1C–08E
IDSH51–04A1F1C–10E
IDSH51-04A1F1C–10F
IDSH51–04A1F1C–10G
IDSH51–04A1F1C–13G
IDSH51–04A1F1C–13H
IDSH51–04A1F1C–13J
IDSH51–04A1F1C–16H
IDSH51–04A1F1C–16J
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-78
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
512 Mbit DDR3 SDRAM Components in
×
8 Organization (64 Mbit
×
8)
512 Mbit DDR3 SDRAM Components in
×
16 Organization (32 Mbit
×
16)
Rev. 0.92, 2008-04
02092007-PWZB-VR0U
4
Advance Internet Data Sheet
IDSH51–0[2/3/4]A1F1C
512-Mbit Double-Data-Rate-Three SDRAM
1.3
DDR3 SDRAM Addressing
TABLE 2
512 Mbit DDR3 SDRAM Addressing
Configuration
Internal Organization
Number of Banks
Bank Address
Row Address
Number of addressable Rows
Column Address
128Mb
×
4
8 banks
×
16 Mbits
×
4
8
BA[2:0]
A[12:0]
8k
A[9:0], A11
64Mb
×
8
8 banks
×
8 Mbits
×
8
8
BA[2:0]
A[12:0]
8k
A[9:0]
1024
1KB
A10 / AP
A12/BC
COLBITS
32Mb
×
16
8 banks
×
4 Mbits
×
16
8
BA[2:0]
A[11:0]
4k
A[9:0]
1024
2KB
A10 / AP
A12/BC
Note
Number of addressable Columns 2048
(page length)
Page Size
Auto-Precharge
Burst length on-the-fly bit
1KB
A10 / AP
A12/BC
1)
2)
1) Page length is the number of addressable columns and is defined as 2
, where COLBITS is the number of column address bits,
excluding A10/AP and A12/BC
2) Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per memory bank and calculated as follows: Page Size = 2
COLBITS
×
ORG/8, where COLBITS is the number of column address
bits and ORG is the number of DQ bits for a given SDRAM configuration (×4,
×8
or
×16).
Rev. 0.92, 2008-04
02092007-PWZB-VR0U
5
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