Preliminary
GS8160Z18/36AT-300/275/250/225/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
-300 -275 -250 -225 -200 Unit
2.2 2.4 2.5 2.7 3.0
ns
3.3 3.6 4.0 4.4 5.0
ns
320
375
320
370
5.0
5.0
220
265
220
265
300
345
300
340
5.25
5.25
215
260
215
260
275
320
275
315
5.5
5.5
210
245
210
245
250
295
250
285
6.0
6.0
200
235
200
235
230
265
225
260
6.5
6.5
190
225
190
225
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
Functional Description
300 MHz–200 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
The GS8160Z18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Pipeline
3-1-1-1
1.8 V
2.5 V
Flow
Through
2-1-1-1
1.8 V
2.5 V
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
Curr
(x18)
Curr
(x36)
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
Read/Write
A
R
B
W
Q
A
C
R
D
B
Q
A
1/25
D
W
Q
C
D
B
E
R
D
D
Q
C
F
W
Q
E
D
D
Q
E
Flow Through
Data I/O
Pipelined
Data I/O
Rev: 1.02a 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8160Z18/36AT-300/275/250/225/200
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
2
–A
18
A
19
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
In
In
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Address Input
Clock Input Signal
Byte Write signal for data inputs DQ
A1
-DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
-DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
-DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
-DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
Core power supply
Ground
Output driver power supply
Rev: 1.02a 9/2002
4/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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