VARIABLE WIDTH SUPERSYNC™ FIFO
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
Integrated Device Technology, Inc.
IDT72264
IDT72274
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Select 8192 x 18 or 16384x 9 organization (IDT72264)
Select 16384 x 18 or 32678 x 9 organization (IDT72274)
Flexible control of read and write clock frequencies
Reduced dynamic power dissipation
Auto power down minimizes power consumption
15 ns read/write cycle time (10 ns access time)
Retransmit Capability
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, full and half-full flags signal FIFO status
Programmable almost empty and almost full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or
First Word Fall Through timing (using
OR
and
IR
flags)
Easily expandable in depth and width
Independent read and write clocks (permits simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
• Industrial temperature range (-40
O
C to +85
O
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72264/72274 are monolithic, CMOS, high capac-
ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs have three
main features that distinguish them among SuperSync FIFOs:
First, the data path width can be changed from 9-bits to 18-
bits; as a result, halving the depth. A pin called Memory Array
Select (MAC) chooses between the two options. This feature
helps reduce the need for redesigns or multiple versions of PC
cards, since a single layout can be used for both data bus
widths.
Second, IDT72264/72274 offer the greatest flexibility for
setting and varying the read and write clock (WCLK and
RCLK) frequencies. For example, given that the two clock
frequencies are unequal, the slower clock may exceed the
faster by, at most, twice its frequency. This feature is espe-
cially useful for communications and network applications
where clock frequencies are switched to permit different data
rates.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
n
LD SEN
•
•
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
•
•
RAM ARRAY
8192 x 18 or 16384 x 9
16384 x 18 or 32768 x 9
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
WRITE POINTER
READ POINTER
•
•
MAC
MEMORY ARRAY
CONFIGURATION
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MRS
PRS
FS
RESET
LOGIC
•
•
•
RCLK
REN
TIMING
OE
COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc
Q
0
-Q
n
3218 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 1997
DSC-3218/2
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
Finally,of all SuperSync FIFOs, the IDT72264/72274 offer
the lowest dynamic power dissipation.
These devices meet a wide variety of data buffering needs.
In addition to those already mentioned, applications include
such as optical disk controllers, Local Area Networks (LANs),
and inter-processor communication.
Both FIFOs have an 18-bit input port (D
n
) and an 18-bit
output port (Q
n
). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (
WEN
). Data is
written into the synchronous FIFO on every clock when
WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (
REN
). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (
OE
) is provided on the read port for three-state
control of the outputs.
The IDT72264/72274 have two modes of operation: In the
IDT Standard Mode
, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the
First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72264/72274 have five flag functions,
EF
/
OR
(Empty Flag or Output Ready),
FF
/
IR
(Full Flag or Input
Ready), and
HF
(Half-full Flag). The
EF
and
FF
functions are
selected in the IDT Standard Mode.
The
IR
and
OR
functions are selected in the First Word Fall
Through Mode.
IR
indicates that the FIFO has free space to
receive data.
OR
indicates that data contained in the FIFO is
available for reading.
HF
is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE
and
PAF
can be programmed independantly to any
point in memory. They, also, can be used irrespective of
mode. Programmable offsets determine the flag threshold
and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, such that
PAE
can be
set at 127 or 1023 locations from the empty boundary and the
PAF
threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with
LD
during Master
Reset
.
PIN CONFIGURATIONS
FWFT/SI
WCLK
PAE
EF
/
OR
GND
PRS
MRS
LD
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
FS
V
CC
MAC
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
REN
RT
OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V
CC
RCLK
FF
/
IR
PAF
HF
Q17
Q16
GND
Q15
Q14
V
CC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
D6
D5
D4
D3
D2
D1
D0
GND
Q0
Q1
GND
Q2
Q3
V
CC
Q4
Q5
3218 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
NOTES
:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D
9
- D
17
may either be tied to ground or left open, Q
9
- Q
17
must be left open.
2
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
In the serial method,
SEN
together with
LD
are used to load
the offset registers via the Serial Input (SI). In the parallel
method,
WEN
together with
LD
can be used to load the offset
registers via D
n
.
REN
together with
LD
can be used to read the
offsets in parallel from Q
n
regardless of whether serial or
parallel offset loading is selected.
During Master Reset (
MRS
), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The
LD
pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (
PRS
) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly.
PRS
is
useful for resetting a device in mid-operation, when repro-
gramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when
RT
is LOW. This feature is convenient for
sending the same data more than once.
If, at any time, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK or WCLK. During the Power Down state, supply current
consumption (I
CC2
) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.
The IDT72264/72274 are depth expandable. The addition
of external components is unnecessary. The
IR
and
OR
functions, together with
REN
and
WEN
, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT72264/72274 is fabricated using IDT’s high speed
submicron CMOS technology.
PIN CONFIGURATIONS (CONT.)
11
10
09
08
07
06
05
DNC Q
5
Q
6
GND Q
4
Q
8
Q
10
Q
7
Q
9
V
CC
Q
2
Q
1
GND D
1
D
0
D
2
D
3
D
4
D
5
D
6
D
9
D
7
D
8
Q
3
GND Q
0
D
11
D
10
D
13
D
12
D
15
D
14
D
17
D
16
Pin 1 Designator
V
CC
MAC
Q
11
GND
Q
13
Q
12
Q
14
V
CC
04 GND Q
15
03
Q
17
Q
16
SEN
FS
02 DNC
01
A
OE REN
GND
PAE HF FF
/ DNC
LD
WCLK
WEN
IR
RT
RCLK
EF
/ V
CC
PAF
GND
FWFT/
MRS PRS
SI
OR
B
C
D
E
F
G
H
J
K
L
3218 drw 03
PGA (G68-1, order code: G)
TOP VIEW
NOTES
:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D
9
- D
17
may be tied to ground or left open, Q
9
- Q
17
must be left open.
2. DNC = Do not connect
3
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D
0
–D
17
Name
Data Inputs
Master Reset
I/O
I
I
Description
Data inputs for a 18-bit bus.
MRS
initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard Mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
Allows data to be resent starting with the first location of FIFO memory.
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
When enabled by
WEN
, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers.
MRS
PRS
RT
FWFT/SI
WCLK
Partial Reset
I
PRS
initializes the read and write pointers to zero and sets the output register to
Retransmit
First Word Fall
Through/Serial In
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
I
I
I
I
I
WEN
RCLK
WEN
enables WCLK for writing data into the FIFO memory and offset registers.
When enabled by
REN
, the rising edge of RCLK reads data from the FIFO
OE
controls the output impedance of Q
n.
SEN
enables serial loading of programmable flag offsets.
During Master Reset,
LD
selects one of two partial flag default offsets (127 and
memory and offsets from the programmable registers.
REN
enables RCLK for reading data from the FIFO memory and offset registers.
REN
OE
SEN
LD
MAC
FS
Memory Array
Configuration
Frequency Select
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost Full Flag
Programmable
Almost Empty
Flag
Half-full Flag
Data Outputs
Power
Ground
I
I
O
1023) and determines programming method, serial or parallel. After Master
Reset, this pin enables writing to and reading from the offset registers.
MAC selects 8192 x 18 or 16384x 9 memory array organization for the IDT72264.
It selects 16384 x 18 or 32678 x 9 memory array organization for the IDT72274.
FF
/
IR
EF
/
OR
PAF
PAE
HF
Q
0
–Q
17
V
CC
GND
O
O
FS selects selects WCLK or RCLK, whichever is running at a higher frequency,
to synchronize the FIFO's internal state machine.
In the IDT Standard Mode, the
FF
function is selected.
FF
indicates whether or
not the FIFO memory is full. In the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to the FIFO memory.
In the IDT Standard Mode, the
EF
function is selected.
EF
indicates whether or
not the FIFO memory is empty. In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the outputs.
PAF
goes HIGH if the number of free locations in the FIFO memory is more than
offset m which is stored in the Full Offset register.
PAF
goes LOW if the
number of free locations in the FIFO memory is less than m.
O
O
O
words in the FIFO memory is greater than offset n.
HF
indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 18-bit bus.
+5 volt power supply pins.
Ground pins.
PAE
goes LOW if the number of words in the FIFO memory is less than offset n
which is stored in the Empty Offset register.
PAE
goes HIGH if the number of
4
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
T
BIAS
T
STG
I
OUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.
Rating
Terminal Voltage
with respect to GND
Operating
Temperature
Temperature Under
Bias
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7.0
0 to +70
–55 to +125
–55 to +125
50
Unit
V
°C
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CCC
GND
Parameter
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Commercial
Min.
4.5
0
2.0
—
Typ.
5.0
0
—
—
Max.
5.5
0
—
0.8
Unit
V
V
V
V
°C
°C
mA
V
IH
V
IL
(1,2)
NOTE:
1. Does not apply to MAC which can only be tied to Vcc or GND.
2. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V
±
10%, T
A
= 0°C to +70°C)
IDT72264L
IDT72274L
Commercial
t
CLK
= 15, 20ns
Symbol
I
LI(1)
I
LO(2)
V
OH
V
OL
I
CC1(3)
I
CC2(3,4)
Parameter
Input Leakage Current (any input except MAC)
Output Leakage Current
Output Logic "1" Voltage, I
OH
= -2mA
Output Logic "0" Voltage, I
OL
= 8mA
MAS = V
CC
Active Power Supply Current
MAS = GND
Power Down Current (All inputs = V
CC
- 0.2V or
GND + 0.2V, RCLK and WCLK are free-running)
—
—
—
—
135
115
mA
mA
Min.
-1
-10
2.4
—
—
Type
—
—
—
—
—
Max
1
10
—
0.4
115
Unit
µA
µA
V
V
mA
NOTES:
1. Measurements with 0.4 < V
IN
< V
CC.
2.
OE
+ V
IH
3. Tested at f = 20 MHz with outputs uploaded.
4. No data written or read for more than 10 cycles.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected, (
OE
=HIGH).
2. Characterized values, not currently tested.
5
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