NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
2Mb
ZBT
®
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High frequency and 100 percent bus utilization
Fast cycle times: 7.5ns and 10ns
Single +3.3V ±5% power supply
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs eliminate
the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin/function compatibility with 4Mb, 8Mb, and
16Mb ZBT SRAM
100-pin TQFP package
Automatic power-down
MT55L128L18P1, MT55L64L32P1,
MT55L64L36P1
3.3V V
DD
, 3.3V I/O
100-Pin TQFP*
*JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
™
(ZBT
®
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
The MT55L128L18P1 and MT55L64L32/36P1
SRAMs integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM
core with advanced synchronous peripheral circuitry
and a 2-bit burst counter. These SRAMs are optimized
for 100 percent bus utilization, eliminating turnaround
cycles for READ to WRITE, or WRITE to READ, transi-
tions. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, chip enable (CE#), two addi-
tional chip enables for easy depth expansion (CE2,
CE2#), cycle start input (ADV/LD#), synchronous clock
enable (CKE#), byte write enables (BWa#, BWb#, BWc#
and BWd#) and read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal minimi-
zation), clock (CLK) and snooze enable (ZZ, which may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q), en-
abled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
OPTIONS
• Timing (Access/Cycle/MHz)
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
128K x 18
64K x 32
64K x 36
• Package
100-pin TQFP
• Temperature
Commercial (0°C to +70°C)
Part Number Example:
MARKING
-7.5
-10
MT55L128L18P1
MT55L64L32P1
MT55L64L36P1
T
None
MT55L128L18P1T-10
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
128K x 18
17
SA0, SA1, SA
MODE
CLK
CKE#
K
ADDRESS
REGISTER 0
17
15
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
17
ADV/LD#
K
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
17
17
ADV/LD#
BWa#
BWb#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
128K x 9 x 2
18
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
18
DQPa
DQPb
E
E
INPUT
REGISTER 1
E
18
INPUT
REGISTER 0
E
18
OE#
CE#
CE2
CE2#
READ LOGIC
FUNCTIONAL BLOCK DIAGRAM
64K x 32/36
16
SA0, SA1, SA
MODE
CLK
CKE#
K
ADDRESS
REGISTER 0
16
14
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
16
ADV/LD#
K
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
16
16
ADV/LD#
BWa#
BWb#
BWc#
BWd#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
36
WRITE
DRIVERS
64K x 8 x 4
(x32)
64K x 9 x 4
(x36)
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
36
DQPa
DQPb
DQPc
DQPd
E
E
INPUT
REGISTER 1
E
36
INPUT
REGISTER 0
E
36
OE#
CE#
CE2
CE2#
READ LOGIC
NOTE:
Functional Block Diagrams illustrate simplified device operation. See truth tables, pin descriptions and
timing diagrams for detailed information.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
GENERAL DESCRIPTION (continued)
All READ, WRITE, and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only avail-
able on the x18 and x36 versions.
Micron’s 2Mb ZBT SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. The device is ideally suited for systems
requiring high bandwidth and zero bus turnaround
delays.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
PIN ASSIGNMENT TABLE
PIN# x18
x32
1
NC
NC
2
NC
DQPc
3
NC
DQc
4
V
DD
Q
5
V
SS
6
NC
DQc
7
NC
DQc
8
DQb
DQc
9
DQb
DQc
10
V
SS
11
V
DD
Q
12
DQb
DQc
13
DQb
DQc
14
V
DD
15
V
DD
16
V
DD
17
V
SS
18
DQb DQd
19
DQb DQd
20
V
DD
Q
21
V
SS
22
DQb DQd
23
DQb DQd
24
DQPb DQd
25
NC
DQd
x36
DQPc
DQPc
DQc
PIN # x18
x32
x36
26
V
SS
27
V
DD
Q
28
NC
DQd DQd
29
NC
DQd DQd
30
NC
NC
DQPd
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
SS
41
V
DD
42
DNU
43
DNU
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
NC/SA*
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x32
NC
DQa
DQa
V
DD
Q
V
SS
NC
DQa
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
V
DD
V
SS
DQa
DQb
DQa
DQb
V
DD
Q
V
SS
DQa
DQb
DQa
DQb
DQPa DQb
NC
DQb
x18
NC
NC
NC
x36
DQa
DQa
DQa
PIN # x18
x32
x36
76
V
SS
77
V
DD
Q
78
NC
DQb DQb
79
NC
DQb DQb
80
SA
NC
DQPb
81
SA
82
SA
83
NF*
84
NF*
85
ADV/LD#
86
OE# (G#)
87
CKE#
88
R/W#
89
CLK
90
V
SS
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC BWc# BWc#
96
NC BWd# BWd#
97
CE2
98
CE#
99
SA
100
SA
DQc
DQc
DQc
DQc
DQa
DQa
DQc
DQc
DQd
DQd
DQb
DQb
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
* Pins 50, 83, and 84 are reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
PIN ASSIGNMENT (Top View)
100-Pin TQFP
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
NC/SA**
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQPb*
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/DQPa*
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
V
DD
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
NC/SA**
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
* NC for x32 version, DQPx for x36 version.
** Pins 50, 83, and 84 are reserved for address expansion.
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
NC/DQPc*
DQPc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
V
DD
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/DQPd*
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
NOT RECOMENDED FOR NEW DESIGNS
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, PIPELINED ZBT SRAM
PIN DESCRIPTIONS
TQFP (x18)
37
36
32–35, 44–49,
80–82, 99, 100
TQFP (x32/x36)
37
36
32–35, 44–49,
81, 82, 99, 100
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are
registered and must meet the setup and hold times
around the rising edge of CLK. Pins 50, 83, and 84 are
reserved as address bits for the higher-density 4Mb,
8Mb, and 16Mb ZBT SRAMs, respectively. SA0 and SA1
are the two least significant bits (LSB) of the address field
and set the internal burst counter if burst is desired.
Synchronous Byte Write Enables: These active LOW
inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold
times around the rising edge of CLK. BWs are associated
with addresses and apply to subsequent data. BYTE
WRITEs need to be asserted on the same cycle as the
address. BWa# controls DQa pins; BWb# controls DQb
pins; BWc# controls DQc pins; BWd# controls DQd pins.
Clock: This signal registers the address, data, chip
enables, byte write enables and burst control inputs on
its rising edge. All synchronous inputs must meet setup
and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Output Enable: This active LOW, asynchronous input
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input
permits CLK to propagate throughout the device. When
CKE# is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This
input must meet setup and hold times around the rising
edge of CLK.
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored.
93
94
–
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE#
(G#)
ADV/LD#
Input
85
85
Input
87
87
CKE#
Input
64
64
ZZ
Input
2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Pipelined ZBT SRAM
MT55L128L18P1_C.p65 – Rev. C, Pub. 11/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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