NB3N201S, NB3N206S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N20xS Series are pure 3.3 V supply differential Multipoint
Low Voltage (M−LVDS) line Drivers and Receivers. Devices
NB3N201S and NB3N206S are TIA/EIA−899 compliant. NB3N201S
offers the Type 1 receiver threshold at 0.0 V. NB3N206S offers the
Type 2 receiver threshold at 0.1 V.
These devices have Type−1 and Type−2 receivers that detect the bus
state with as little as 50 mV of differential input voltage over a
common−mode voltage range of −1 V to 3.4 V. The Type−1 receivers
have near zero thresholds (±50 mV) and exhibit 25 mV of differential
input voltage hysteresis to prevent output oscillations with slowly
changing signals or loss of input. Type−2 receivers include an offset
threshold to provide a detectable voltage under open−circuit, idle−bus,
and other faults conditions.
NB3N201S and NB3N206S support Simplex or Half Duplex bus
configurations.
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MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
NB20x
x
A
Y
WW
G or
G
NB20x
AYWW
G
1
8
= Specific Device Code
= 1, 6
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
Features
•
Low−Voltage Differential 30
W
to 55
W
Line Drivers
•
•
•
•
•
•
and Receivers for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Type−2 Receivers Provide an Offset (100 mV)
Threshold to Detect Open−Circuit and Idle−Bus
Conditions
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or VCC
≤
1.5 V
•
•
•
•
M−LVDS Bus Power Up/Down Glitch Free
Operating range: VCC = 3.3
±10%
V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
These are Pb−Free Devices
Applications
•
Low−Power High−Speed Short−Reach Alternative to
•
•
•
•
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
©
Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 1
Publication Order Number:
NB3N201S/D
NB3N201S, NB3N206S
R
RE
1
8 V
CC
7 B
2
DE
3
6 A
D
4
5 GND
SOIC−8
NB3N201S, NB3N206S
Figure 1. Logic Diagram
Figure 2. Pinout Diagram
(Top View)
Table 1. PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
Name
R
RE
DE
D
GND
A
B
VCC
M−LVDS Input
/Output
M−LVDS Input
/Output
I/O Type
LVCMOS Output
LVCMOS Input
LVCMOS Input
LVCMOS Input
High
Low
Open Default
Receiver Output Pin
Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
Driver Enable Input Pin (LOW = High Z Output, HIGH=Active)
Driver Input Pin
Ground Supply pin. Pin must be connected to power supply to
guarantee proper operation.
Transceiver True Input /Output Pin
Transceiver Invert Input /Output Pin
Power Supply pin. Pin must be connected to power supply to
guarantee proper operation.
Description
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NB3N201S, NB3N206S
Table 2. DEVICE FUNCTION TABLE
Inputs
V
ID
= V
A
− V
B
V
ID
w
50 mV
TYPE 1 Receiver
(NB3N201/NB3N203)
−50 mV < V
ID
< 50 mV
V
ID
≤
−50 mV
X
X
Open
Inputs
V
ID
= V
A
− V
B
V
ID
w
150 mV
TYPE 2 Receiver
(NB3N206/NB3N207)
50 mV < V
ID
< 150 mV
V
ID
≤
50 mV
X
X
Open
Input
D
L
DRIVER
H
Open
X
X
RE
L
L
L
H
Open
L
Enable
DE
H
H
H
Open
L
A/Y
L
H
L
Z
Z
RE
L
L
L
H
Open
L
Output
R
H
?
L
Z
Z
?
Output
R
H
?
L
Z
Z
L
Output
B/Z
H
L
H
Z
Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
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NB3N201S, NB3N206S
Table 3. ATTRIBUTES
(Note 1)
Characteristics
Human Body Model (JEDEC
Standard 22, Method A114−A)
ESD
Protection
Machine Model
Charged –Device Model (JEDEC
Standard 22, Method C101)
A, B, Y, Z
All Pins
All Pins
All Pins
Value
±6
kV
±2
kV
±200
V
±1500
V
Level 1
UL−94 code V−0 A 1/8”
28 to 34
917 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
IN
Supply Voltage
Input Voltage
D, DE, RE
A, B (201, 206)
I
OUT
Parameter
Condition 1
Condition 2
Rating
−0.5
≤
V
CC
≤
4.0
−0.5
≤
V
IN
≤
4.0
−1.8
≤
V
IN
≤
4.0
−0.3
≤
I
OUT
≤
4.0
−1.8
≤
I
OUT
≤
4.0
−40 to
≤
+85
−65 to +150
Unit
V
V
Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Power Dissipation (Continuous)
R
A, B
V
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
mW
mW/°C
mW
T
A
T
stg
θ
JA
θ
JC
θ
JA
q
JC
T
sol
P
D
0 lfpm
500 lfpm
(Note 3)
0 lfpm
500 lfpm
(Note 3)
SOIC−8
SOIC−8
SOIC−14
SOIC−14
190
130
41 to 44
80
36
265
T
A
= 25°C
25°C < T
A
< 85°C
T
A
= 85°C
725
5.8
377
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3N201S, NB3N206S
Table 5. DC CHARACTERISTICS
VCC = 3.3
±10%
V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (See Notes 4, 5)
Symbol
ICC
Characteristic
Power Supply Current
Receiver Disabled Driver Enabled RE and DE at V
CC
, R
L
= 50
W,
All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, R
L
= No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at V
CC
, R
L
= 50
W,
All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, R
L
= 50
W,
All others open
Input HIGH Voltage
Input LOW Voltage
Voltage at any bus terminal VA, VB, VY or VZ
Magnitude of differential input voltage
Differential output voltage magnitude (see Figure 4)
Change in Differential output voltage magnitude between logic states (see Figure 4)
Steady state common mode output voltage (see Figure 5)
Change in Steady state common mode output voltage between logic states (see
Figure 5)
Peak−to−peak common−mode output voltage (see Figure 5)
Maximum steady−state open−circuit output voltage (see Figure 9)
Maximum steady−state open−circuit output voltage (see Figure 9)
Voltage overshoot, low−to−high level output (see Figure 7)
Voltage overshoot, high−to−low level output (see Figure 7)
High−level input current (D, DE) V
IH
= 2 V
Low−level input current (D, DE) V
IL
= 0.8 V
Differential short−circuit output current magnitude (see Figure 6)
High−impedance state output current (driver only)
−1.4 V
≤
(VA or VB)
≤
3.8 V, other output at 1.2 V
Power−off output current (0 V
≤
V
CC
≤
1.5 V)
−1.4 V
≤
(VA or VB)
≤
3.8 V, other output at 1.2 V
Positive−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
Type 1
Type 2
Negative−going Differential Input voltage Threshold (See Figure 11 & Tables 8 and 9)
Type 1
Type 2
Differential Input Voltage Hysteresis (See Figure 11 and Table 2)
Type 1
Type 2
VOH
VOL
I
IH
I
IL
I
OZ
C
A
/ C
B
C
AB
C
A/B
High−level output voltage (IOH = –8 mA
Low−level output voltage (IOL = 8 mA)
RE
High-level
input current (VIH = 2 V)
RE
Low-level
input current (VIL = 0.8 V)
High−impedance state output current (VO = 0 V of 3.6 V)
Input Capacitance VI = 0.4
impedance analyzer (or equivalent)
sin(30E
6
πt)
+ 0.5 V, other outputs at 1.2 V using HP4194A
−10
−10
−10
3
2.5
99
101
2.4
0.4
0
0
15
25
0
V
V
mA
mA
mA
pF
pF
%
−50
50
mV
−15
−10
−0.2 V
SS
0
0
10
10
24
10
10
0
0
2
GND
−1.4
0.05
480
−50
0.8
−50
Min
Typ
13
1
16
Max
22
4
24
13
V
CC
0.8
3.8
V
CC
650
50
1.2
50
150
2.4
2.4
1.2 V
SS
mV
mV
V
mV
mV
V
V
V
V
uA
uA
mA
uA
uA
V
V
V
Unit
mA
V
IH
V
IL
VBUS
|VID|
DRIVER
|V
AB
|
D|V
AB
|
V
OS(SS)
DV
OS(SS)
V
OS(PP)
V
AOC
V
BOC
V
P(H)
V
P(L)
I
IH
I
IL
JI
OS
J
I
OZ
I
O(OFF)
RECEIVER
V
IT+
mV
50
150
mV
V
IT−
V
HYS
Differential Input Capacitance V
AB
= 0.4 sin(30E
6
πt)
V, other outputs at 1.2 V using
HP4194A impedance analyzer (or equivalent)
Input Capacitance Balance, (C
A
/C
B
)
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