Simplifying System Integration
TM
73M1903C
Evaluation Board User Manual
June 12, 2009
Rev. 2.0
UM_1903C_030
73M1903C Evaluation Board User Manual
UM_1903C_030
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
2
Rev. 2.0
UM_1903C_030
73M1903C Evaluation Board User Manual
Table of Contents
Introduction ................................................................................................................................... 5
Safety and ESD Notes .......................................................................................................... 5
1.1
Evaluation Board Host Interfaces .......................................................................................... 5
1.2
2
System Description ....................................................................................................................... 6
MAFE Interface ..................................................................................................................... 7
2.1
73M1903C Register Map ...................................................................................................... 9
2.2
73M1903C System Initialization ............................................................................................ 9
2.3
Typical Sample Rate Settings ............................................................................................. 11
2.4
3
Hardware Description .................................................................................................................. 12
Board Settings: Jumpers and Connectors ........................................................................... 12
3.1
Board Physical and Operating Information .......................................................................... 16
3.2
4
73M1903C Evaluation Board Schematics, PCB Layouts and Bill of Materials.......................... 17
Schematic........................................................................................................................... 17
4.1
PCB Layouts....................................................................................................................... 18
4.2
Bill of Materials ................................................................................................................... 21
4.3
5
Ordering Information ................................................................................................................... 23
6
Related Documentation ............................................................................................................... 23
7
Contact Information..................................................................................................................... 23
Revision History .................................................................................................................................. 23
1
Rev. 2.0
3
73M1903C Evaluation Board User Manual
UM_1903C_030
Figures
Figure 1: 73M1903C Evaluation Board..................................................................................................... 5
Figure 2: 73M1903C Evaluation Board Block Diagram ............................................................................. 6
Figure 3: 73M1903C in Master or Slave Configuration ............................................................................. 7
Figure 4: 73M1903C Daisy Chain Configurations ..................................................................................... 7
Figure 5: MAFE Timing Diagram .............................................................................................................. 8
Figure 6: Serial Data Timing .................................................................................................................... 8
Figure 7: 73M1903C Evaluation Board Jumpers and Connectors ........................................................... 12
Figure 8: 73M1903C Evaluation Board PCB Dimensions ....................................................................... 16
Figure 9: 73M1903C Evaluation Board Electrical Schematic .................................................................. 17
Figure 10: 73M1903C Evaluation Board Silk Screen Top ....................................................................... 18
Figure 11: 73M1903C Evaluation Board Top Signal Layer ..................................................................... 19
Figure 12: 73M1903C Evaluation Board Layer 2 – Ground Plane........................................................... 19
Figure 13: 73M1903C Evaluation Board Layer 3 – Supply Plane............................................................ 20
Figure 14: 73M1903C Evaluation Board Bottom Signal Layer ................................................................ 20
Tables
Table 1: 73M1903C Register Memory Map .............................................................................................. 9
Table 2: Control Register Settings for Example Sample Rates ............................................................... 11
Table 3: 73M1903C Evaluation Board Connectors ................................................................................. 12
Table 4: JP25 Pin Assignments ............................................................................................................. 13
Table 5: 73M1903C Evaluation Board Jumper Description ..................................................................... 13
Table 6: 73M1903C Evaluation Board Bill of Materials ........................................................................... 21
4
Rev. 2.0
UM_1903C_030
73M1903C Evaluation Board User Manual
1 Introduction
The Teridian Semiconductor Corporation (TSC) 73M1903C Evaluation Board is a Modem Analog Front
End Evaluation Board with an on-board DAA for evaluating the 73M1903C device. This device can
support up to V.90 modulation and demodulation on typical DSP or CPU systems available in the market.
The 73M1903C Evaluation Board incorporates a 73M1903C integrated circuit, a US, CTR21 or World
Wide DAA circuit for interfacing with the telephone line and an audio amplifier and speaker for line
monitoring during the call progress period. The Evaluation Board supports the evaluation of the
73M1903C Modem Analog Front End device for universal modem applications and interfaces to a general
purpose DSP or CPU system.
Figure 1: 73M1903C Evaluation Board
1.1
Safety and ESD Notes
THE 73M1903C EVALUATION BOARD IS ESD SENSITIVE! ESD PRECAUTIONS
SHOULD BE TAKEN WHEN HANDLING THE EVALUATION BOARD!
1.2
Evaluation Board Host Interfaces
The 73M1903C Evaluation Board includes a Modem Analog Front End (MAFE) Interface with a 20-pin
right angle connector to connect to a target DSP or CPU system. The Evaluation Board also includes a
3.3 V power receptacle for powering the on board circuits from either the target system or an external
power supply.
Rev. 2.0
5
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
