4Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)
SDRAM data sheet specifications when running in
1.5V compatible mode.
• T
C
of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Features
• V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
• Backward compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
– Supports DDR3L devices to be backward com-
patible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
Options
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (10.5mm x 12mm) Rev. D
– 78-ball (9mm x 10.5mm) Rev. E, J
• FBGA package (Pb-free) – x16
– 96-ball (10mm x 14mm) Rev. D
– 96-ball (9mm x 14mm) Rev. E
• Timing – cycle time
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Marking
1G4
512M8
256M16
RA
RH
RE
HA
-107
-125
-15E
-187E
None
IT
:D/:E/:J
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2, 3
-125
1, 2
-15E
1
-187E
Notes:
Data Rate (MT/s)
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
Page size
1 Gig x 4
128 Meg x 4 x 8 banks
8K
64K (A[15:0])
8 (BA[2:0])
2K (A[11, 9:0])
1KB
512 Meg x 8
64 Meg x 8 x 8 banks
8K
64K (A[15:0])
8 (BA[2:0])
1K (A[9:0])
1KB
256 Meg x 16
32 Meg x 16 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3L Part Numbers
Example Part Number:
MT41K512M8RH-125:E
-
MT41K
Configuration
Package
Speed
:
Revision
{
:D/:E/:J/:Q Revision
Temperature
1G4
512M8
256M16
Speed Grade
Package
78-ball 10.5mm x 12mm FBGA
78-ball 9mm x 10.5mm FBGA
96-ball 10.0mm x 14mm FBGA
96-ball 9mm x 14mm FBGA
Rev.
D
E, J, Q
D
E, Q
Mark
RA
RH
RE
HA
-107
-125
-15E
-187E
t
CK
t
CK
t
CK
t
CK
Configuration
1 Gig x 4
512 Meg x 8
256 Meg x 16
Commercial
Industrial temperature
None
IT
= 1.071ns, CL = 13
= 1.25ns, CL = 11
= 1.5ns, CL = 9
= 1.875ns, CL = 7
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com
for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 30
Electrical Characteristics – DDR3L (1.35V) Operating I
DD
Specifications ........................................................... 41
Electrical Specifications – DC and AC .............................................................................................................. 45
DC Operating Conditions ........................................................................................................................... 45
Input Operating Conditions ........................................................................................................................ 46
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 50
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 53
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 55
ODT Characteristics ....................................................................................................................................... 56
1.35V ODT Resistors ................................................................................................................................... 57
ODT Sensitivity .......................................................................................................................................... 58
ODT Timing Definitions ............................................................................................................................. 58
Output Driver Impedance ............................................................................................................................... 62
34 Ohm Output Driver Impedance .............................................................................................................. 63
DDR3L 34 Ohm Driver ................................................................................................................................ 64
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 65
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 66
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 66
Output Characteristics and Operating Conditions ............................................................................................ 68
Reference Output Load ............................................................................................................................... 71
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 71
Slew Rate Definitions for Differential Output Signals .................................................................................... 73
Speed Bin Tables ............................................................................................................................................ 74
Electrical Characteristics and AC Operating Conditions ................................................................................... 78
Command and Address Setup, Hold, and Derating ........................................................................................... 98
Data Setup, Hold, and Derating ...................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 113
Commands ................................................................................................................................................... 116
DESELECT ................................................................................................................................................ 116
NO OPERATION ........................................................................................................................................ 116
ZQ CALIBRATION LONG ........................................................................................................................... 116
ZQ CALIBRATION SHORT .......................................................................................................................... 116
ACTIVATE ................................................................................................................................................. 116
READ ........................................................................................................................................................ 116
WRITE ...................................................................................................................................................... 117
PRECHARGE ............................................................................................................................................. 118
REFRESH .................................................................................................................................................. 118
SELF REFRESH .......................................................................................................................................... 119
DLL Disable Mode ..................................................................................................................................... 120
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
Input Clock Frequency Change ...................................................................................................................... 124
Write Leveling ............................................................................................................................................... 126
Write Leveling Procedure ........................................................................................................................... 128
Write Leveling Mode Exit Procedure ........................................................................................................... 130
Initialization ................................................................................................................................................. 131
Voltage Initialization / Change ....................................................................................................................... 133
V
DD
Voltage Switching ............................................................................................................................... 134
Mode Registers .............................................................................................................................................. 135
Mode Register 0 (MR0) ................................................................................................................................... 136
Burst Length ............................................................................................................................................. 136
Burst Type ................................................................................................................................................. 137
DLL RESET ................................................................................................................................................ 138
Write Recovery .......................................................................................................................................... 138
Precharge Power-Down (Precharge PD) ...................................................................................................... 139
CAS Latency (CL) ....................................................................................................................................... 139
Mode Register 1 (MR1) ................................................................................................................................... 140
DLL Enable/DLL Disable ........................................................................................................................... 140
Output Drive Strength ............................................................................................................................... 141
OUTPUT ENABLE/DISABLE ...................................................................................................................... 141
TDQS Enable ............................................................................................................................................. 141
On-Die Termination .................................................................................................................................. 142
WRITE LEVELING ..................................................................................................................................... 142
POSTED CAS ADDITIVE Latency ................................................................................................................ 142
Mode Register 2 (MR2) ................................................................................................................................... 143
CAS Write Latency (CWL) ........................................................................................................................... 144
AUTO SELF REFRESH (ASR) ....................................................................................................................... 144
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 145
SRT vs. ASR ............................................................................................................................................... 145
DYNAMIC ODT ......................................................................................................................................... 145
Mode Register 3 (MR3) ................................................................................................................................... 146
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146
MPR Functional Description ...................................................................................................................... 147
MPR Register Address Definitions and Bursting Order ................................................................................. 148
MPR Read Predefined Pattern .................................................................................................................... 154
MODE REGISTER SET (MRS) Command ........................................................................................................ 154
ZQ CALIBRATION Operation ......................................................................................................................... 155
ACTIVATE Operation ..................................................................................................................................... 156
READ Operation ............................................................................................................................................ 158
WRITE Operation .......................................................................................................................................... 169
DQ Input Timing ....................................................................................................................................... 177
PRECHARGE Operation ................................................................................................................................. 179
SELF REFRESH Operation .............................................................................................................................. 179
Extended Temperature Usage ........................................................................................................................ 181
Power-Down Mode ........................................................................................................................................ 182
RESET Operation ........................................................................................................................................... 190
On-Die Termination (ODT) ............................................................................................................................ 192
Functional Representation of ODT ............................................................................................................. 192
Nominal ODT ............................................................................................................................................ 192
Dynamic ODT ............................................................................................................................................... 194
Dynamic ODT Special Use Case ................................................................................................................. 194
Functional Description .............................................................................................................................. 194
Synchronous ODT Mode ................................................................................................................................ 200
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
ODT Latency and Posted ODT .................................................................................................................... 200
Timing Parameters .................................................................................................................................... 200
ODT Off During READs .............................................................................................................................. 203
Asynchronous ODT Mode .............................................................................................................................. 205
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 207
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 209
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 211
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
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