Datasheet> 器件分类 > 存储> 存储> MT41K256M16HA-125AIT

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MT41K256M16HA-125AIT: 产品描述DDR DRAM, 256MX16, CMOS, PBGA96, 10 X 14 MM, LEAD FREE, FBGA-96; 产品类别存储存储; 文件大小3MB，共213页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT41K256M16HA-125AIT概述

DDR DRAM, 256MX16, CMOS, PBGA96, 10 X 14 MM, LEAD FREE, FBGA-96

MT41K256M16HA-125AIT规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Micron Technology
包装说明	TFBGA,
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	MULTI BANK PAGE BURST
其他特性	AUTO/SELF REFRESH
JESD-30 代码	R-PBGA-B96
长度	14 mm
内存密度	4294967296 bit
内存集成电路类型	DDR DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	96
字数	268435456 words
字数代码	256000000
工作模式	SYNCHRONOUS
组织	256MX16
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
座面最大高度	1.2 mm
自我刷新	YES
最大供电电压 (Vsup)	1.45 V
最小供电电压 (Vsup)	1.283 V
标称供电电压 (Vsup)	1.35 V
表面贴装	YES
技术	CMOS
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	9 mm

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4Gb: x4, x8, x16 DDR3L SDRAM

Description

DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks

MT41K512M8 – 64 Meg x 8 x 8 banks

MT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the

DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)

SDRAM data sheet specifications when running in

1.5V compatible mode.

• T

of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C

– 32ms at +85°C to +95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

Features

• V

= V

DDQ

= 1.35V (1.283–1.45V)

• Backward compatible to V

= V

DDQ

= 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

Options

• Configuration

– 1 Gig x 4

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (10.5mm x 12mm) Rev. D

– 78-ball (9mm x 10.5mm) Rev. E, J

• FBGA package (Pb-free) – x16

– 96-ball (10mm x 14mm) Rev. D

– 96-ball (9mm x 14mm) Rev. E

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.875ns @ CL = 7 (DDR3-1066)

• Operating temperature

– Commercial (0°C

≤

+95°C)

– Industrial (–40°C

≤

+95°C)

• Revision

Marking

1G4

512M8

256M16

-107

-125

-15E

-187E

None

:D/:E/:J

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2, 3

-125

1, 2

-15E

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL = 11 (-125).

PDF: 09005aef84780270

4Gb_DDR3L.pdf - Rev. I 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x4, x8, x16 DDR3L SDRAM

Description

Contents

State Diagram ................................................................................................................................................ 11

Functional Description ................................................................................................................................... 12

Industrial Temperature ............................................................................................................................... 12

General Notes ............................................................................................................................................ 12

Functional Block Diagrams ............................................................................................................................. 14

Ball Assignments and Descriptions ................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 22

Electrical Specifications .................................................................................................................................. 26

Absolute Ratings ......................................................................................................................................... 26

Input/Output Capacitance .......................................................................................................................... 27

Thermal Characteristics .................................................................................................................................. 28

Electrical Specifications – I

Specifications and Conditions ............................................................................ 30

Electrical Characteristics – DDR3L (1.35V) Operating I

Specifications ........................................................... 41

Electrical Specifications – DC and AC .............................................................................................................. 45

DC Operating Conditions ........................................................................................................................... 45

Input Operating Conditions ........................................................................................................................ 46

DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 50

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 53

DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 55

ODT Characteristics ....................................................................................................................................... 56

1.35V ODT Resistors ................................................................................................................................... 57

ODT Sensitivity .......................................................................................................................................... 58

ODT Timing Definitions ............................................................................................................................. 58

Output Driver Impedance ............................................................................................................................... 62

34 Ohm Output Driver Impedance .............................................................................................................. 63

DDR3L 34 Ohm Driver ................................................................................................................................ 64

DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 65

DDR3L Alternative 40 Ohm Driver ............................................................................................................... 66

DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 66

Output Characteristics and Operating Conditions ............................................................................................ 68

Reference Output Load ............................................................................................................................... 71

Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 71

Slew Rate Definitions for Differential Output Signals .................................................................................... 73

Speed Bin Tables ............................................................................................................................................ 74

Electrical Characteristics and AC Operating Conditions ................................................................................... 78

Command and Address Setup, Hold, and Derating ........................................................................................... 98

Data Setup, Hold, and Derating ...................................................................................................................... 105

Commands – Truth Tables ............................................................................................................................. 113

Commands ................................................................................................................................................... 116

DESELECT ................................................................................................................................................ 116

NO OPERATION ........................................................................................................................................ 116

ZQ CALIBRATION LONG ........................................................................................................................... 116

ZQ CALIBRATION SHORT .......................................................................................................................... 116

ACTIVATE ................................................................................................................................................. 116

READ ........................................................................................................................................................ 116

WRITE ...................................................................................................................................................... 117

PRECHARGE ............................................................................................................................................. 118

REFRESH .................................................................................................................................................. 118

SELF REFRESH .......................................................................................................................................... 119

DLL Disable Mode ..................................................................................................................................... 120

PDF: 09005aef84780270

4Gb_DDR3L.pdf - Rev. I 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR3L SDRAM

Description

Input Clock Frequency Change ...................................................................................................................... 124

Write Leveling ............................................................................................................................................... 126

Write Leveling Procedure ........................................................................................................................... 128

Write Leveling Mode Exit Procedure ........................................................................................................... 130

Initialization ................................................................................................................................................. 131

Voltage Initialization / Change ....................................................................................................................... 133

Voltage Switching ............................................................................................................................... 134

Mode Registers .............................................................................................................................................. 135

Mode Register 0 (MR0) ................................................................................................................................... 136

Burst Length ............................................................................................................................................. 136

Burst Type ................................................................................................................................................. 137

DLL RESET ................................................................................................................................................ 138

Write Recovery .......................................................................................................................................... 138

Precharge Power-Down (Precharge PD) ...................................................................................................... 139

CAS Latency (CL) ....................................................................................................................................... 139

Mode Register 1 (MR1) ................................................................................................................................... 140

DLL Enable/DLL Disable ........................................................................................................................... 140

Output Drive Strength ............................................................................................................................... 141

OUTPUT ENABLE/DISABLE ...................................................................................................................... 141

TDQS Enable ............................................................................................................................................. 141

On-Die Termination .................................................................................................................................. 142

WRITE LEVELING ..................................................................................................................................... 142

POSTED CAS ADDITIVE Latency ................................................................................................................ 142

Mode Register 2 (MR2) ................................................................................................................................... 143

CAS Write Latency (CWL) ........................................................................................................................... 144

AUTO SELF REFRESH (ASR) ....................................................................................................................... 144

SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 145

SRT vs. ASR ............................................................................................................................................... 145

DYNAMIC ODT ......................................................................................................................................... 145

Mode Register 3 (MR3) ................................................................................................................................... 146

MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146

MPR Functional Description ...................................................................................................................... 147

MPR Register Address Definitions and Bursting Order ................................................................................. 148

MPR Read Predefined Pattern .................................................................................................................... 154

MODE REGISTER SET (MRS) Command ........................................................................................................ 154

ZQ CALIBRATION Operation ......................................................................................................................... 155

ACTIVATE Operation ..................................................................................................................................... 156

READ Operation ............................................................................................................................................ 158

WRITE Operation .......................................................................................................................................... 169

DQ Input Timing ....................................................................................................................................... 177

PRECHARGE Operation ................................................................................................................................. 179

SELF REFRESH Operation .............................................................................................................................. 179

Extended Temperature Usage ........................................................................................................................ 181

Power-Down Mode ........................................................................................................................................ 182

RESET Operation ........................................................................................................................................... 190

On-Die Termination (ODT) ............................................................................................................................ 192

Functional Representation of ODT ............................................................................................................. 192

Nominal ODT ............................................................................................................................................ 192

Dynamic ODT ............................................................................................................................................... 194

Dynamic ODT Special Use Case ................................................................................................................. 194

Functional Description .............................................................................................................................. 194

Synchronous ODT Mode ................................................................................................................................ 200

PDF: 09005aef84780270

4Gb_DDR3L.pdf - Rev. I 9/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT41K256M16HA-125AIT相似产品对比

	MT41K256M16HA-125AIT	MT41K512M8RH-125AIT	MT41K256M16HA-125:E	MT41K512M8RH-125:E	MT41K1G4RH-125:E	MT41K256M16HA-125IT	MT41K256M16HA-125M	MT41K512M8RH-125IT	MT41K512M8RH-107:E	MT41K512M8RH-125M
描述	DDR DRAM, 256MX16, CMOS, PBGA96, 10 X 14 MM, LEAD FREE, FBGA-96	DDR DRAM, 512KX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 256MX16, CMOS, PBGA96, 9 X 14 MM, LEAD FREE, FBGA-96	DDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 1GX4, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 256MX16, CMOS, PBGA96, 10 X 14 MM, LEAD FREE, FBGA-96	DDR DRAM, 256MX16, CMOS, PBGA96, 10 X 14 MM, LEAD FREE, FBGA-96	DDR DRAM, 512KX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 512MX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78	DDR DRAM, 512KX8, CMOS, PBGA78, 9 X 10.50 MM, LEAD FREE, FBGA-78
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	符合	符合
厂商名称	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
包装说明	TFBGA,	TFBGA,	TFBGA, BGA96,9X16,32	TFBGA, BGA78,9X13,32	TFBGA, BGA78,9X13,32	TFBGA,	TFBGA,	TFBGA,	TFBGA, BGA78,9X13,32	TFBGA,
Reach Compliance Code	compliant	compliant	not_compliant	not_compliant	compliant	compliant	compliant	compliant	not_compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH, ALSO OPERATES AT 1.5V SUPPLY	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 代码	R-PBGA-B96	R-PBGA-B78	R-PBGA-B96	R-PBGA-B78	R-PBGA-B78	R-PBGA-B96	R-PBGA-B96	R-PBGA-B78	R-PBGA-B78	R-PBGA-B78
长度	14 mm	10.5 mm	14 mm	10.5 mm	10.5 mm	14 mm	14 mm	10.5 mm	10.5 mm	10.5 mm
内存密度	4294967296 bit	4194304 bit	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit	4194304 bit	4294967296 bit	4194304 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	16	8	16	8	4	16	16	8	8	8
功能数量	1	1	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1	1	1
端子数量	96	78	96	78	78	96	96	78	78	78
字数	268435456 words	524288 words	268435456 words	536870912 words	1073741824 words	268435456 words	268435456 words	524288 words	536870912 words	524288 words
字数代码	256000000	512000	256000000	512000000	1000000000	256000000	256000000	512000	512000000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
组织	256MX16	512KX8	256MX16	512MX8	1GX4	256MX16	256MX16	512KX8	512MX8	512KX8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V
最小供电电压 (Vsup)	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V
标称供电电压 (Vsup)	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	260	260	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	30	30	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED

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