2Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K512M4 – 64 Meg x 4 x 8 banks
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
•
•
•
•
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Options
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm)
Rev. M, K
– 78-ball FBGA (9mm x 11.5mm)
Rev. D
• FBGA package (Pb-free) – x16
– 96-ball FBGA (9mm x 14mm)
Rev. D
– 96-ball FBGA (8mm x 14mm)
Rev. K
• Timing – cycle time
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Marking
512M4
256M8
128M16
DA
HX
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
Backward-compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
Self refresh temperature (SRT)
HA
JT
-107
-125
-15E
-187E
None
IT
:D/ :M / :K
•
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2, 3
-125
1, 2
-15E
1
-187E
Notes:
Data Rate (MT/s)
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
13.91
13.75
13.5
13.1
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-107).
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
Row address
Bank address
Column address
512 Meg x 4
64 Meg x 4 x 8 banks
8K
32K A[14:0]
8 BA[2:0]
2K A[11, 9:0]
256 Meg x 8
32 Meg x 8 x 8 banks
8K
32K A[14:0]
8 BA[2:0]
1K A[9:0]
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K A[13:0]
8 BA[2:0]
1K A[9:0]
Figure 1: DDR3L Part Numbers
Example Part Number:
MT41K256M8DA-125:K
-
MT41K
Configuration
Package
Speed
:
Revision
{
:D/:M/:K
Configuration
512 Meg x 4
256 Meg x 8
128 Meg x 16
512M4
256M8
128M16
Temperature
Commercial
Industrial temperature
None
IT
Revision
Package
78-ball 9mm x 11.5mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 9mm x 14mm FBGA
96-ball 8mm x 14mm FBGA
HX
DA
HA
JT
-107
-125
-15E
-187E
Speed Grade
tCK = 1.071ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com
for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM
Description
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 30
Electrical Characteristics – I
DD
Specifications .................................................................................................. 41
Electrical Specifications – DC and AC .............................................................................................................. 44
DC Operating Conditions ........................................................................................................................... 44
Input Operating Conditions ........................................................................................................................ 45
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 49
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 52
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 54
ODT Characteristics ....................................................................................................................................... 55
1.35V ODT Resistors ................................................................................................................................... 56
ODT Sensitivity .......................................................................................................................................... 57
ODT Timing Definitions ............................................................................................................................. 57
Output Driver Impedance ............................................................................................................................... 61
34 Ohm Output Driver Impedance .............................................................................................................. 62
DDR3L 34 Ohm Driver ................................................................................................................................ 63
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 64
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 65
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 65
Output Characteristics and Operating Conditions ............................................................................................ 67
Reference Output Load ............................................................................................................................... 70
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 70
Slew Rate Definitions for Differential Output Signals .................................................................................... 72
Speed Bin Tables ............................................................................................................................................ 73
Electrical Characteristics and AC Operating Conditions ................................................................................... 77
Command and Address Setup, Hold, and Derating ........................................................................................... 97
Data Setup, Hold, and Derating ...................................................................................................................... 104
Commands – Truth Tables ............................................................................................................................. 112
Commands ................................................................................................................................................... 115
DESELECT ................................................................................................................................................ 115
NO OPERATION ........................................................................................................................................ 115
ZQ CALIBRATION LONG ........................................................................................................................... 115
ZQ CALIBRATION SHORT .......................................................................................................................... 115
ACTIVATE ................................................................................................................................................. 115
READ ........................................................................................................................................................ 115
WRITE ...................................................................................................................................................... 116
PRECHARGE ............................................................................................................................................. 117
REFRESH .................................................................................................................................................. 117
SELF REFRESH .......................................................................................................................................... 118
DLL Disable Mode ..................................................................................................................................... 119
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM
Description
Input Clock Frequency Change ...................................................................................................................... 123
Write Leveling ............................................................................................................................................... 125
Write Leveling Procedure ........................................................................................................................... 127
Write Leveling Mode Exit Procedure ........................................................................................................... 129
Initialization ................................................................................................................................................. 130
Voltage Initialization / Change ....................................................................................................................... 132
V
DD
Voltage Switching ............................................................................................................................... 133
Mode Registers .............................................................................................................................................. 134
Mode Register 0 (MR0) ................................................................................................................................... 135
Burst Length ............................................................................................................................................. 135
Burst Type ................................................................................................................................................. 136
DLL RESET ................................................................................................................................................ 137
Write Recovery .......................................................................................................................................... 137
Precharge Power-Down (Precharge PD) ...................................................................................................... 138
CAS Latency (CL) ....................................................................................................................................... 138
Mode Register 1 (MR1) ................................................................................................................................... 139
DLL Enable/DLL Disable ........................................................................................................................... 139
Output Drive Strength ............................................................................................................................... 140
OUTPUT ENABLE/DISABLE ...................................................................................................................... 140
TDQS Enable ............................................................................................................................................. 140
On-Die Termination .................................................................................................................................. 141
WRITE LEVELING ..................................................................................................................................... 141
POSTED CAS ADDITIVE Latency ................................................................................................................ 141
Mode Register 2 (MR2) ................................................................................................................................... 142
CAS Write Latency (CWL) ........................................................................................................................... 143
AUTO SELF REFRESH (ASR) ....................................................................................................................... 143
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144
SRT vs. ASR ............................................................................................................................................... 144
DYNAMIC ODT ......................................................................................................................................... 144
Mode Register 3 (MR3) ................................................................................................................................... 145
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 145
MPR Functional Description ...................................................................................................................... 146
MPR Register Address Definitions and Bursting Order ................................................................................. 147
MPR Read Predefined Pattern .................................................................................................................... 153
MODE REGISTER SET (MRS) Command ........................................................................................................ 153
ZQ CALIBRATION Operation ......................................................................................................................... 154
ACTIVATE Operation ..................................................................................................................................... 155
READ Operation ............................................................................................................................................ 157
WRITE Operation .......................................................................................................................................... 168
DQ Input Timing ....................................................................................................................................... 176
PRECHARGE Operation ................................................................................................................................. 178
SELF REFRESH Operation .............................................................................................................................. 178
Extended Temperature Usage ........................................................................................................................ 180
Power-Down Mode ........................................................................................................................................ 181
RESET Operation ........................................................................................................................................... 189
On-Die Termination (ODT) ............................................................................................................................ 191
Functional Representation of ODT ............................................................................................................. 191
Nominal ODT ............................................................................................................................................ 191
Dynamic ODT ............................................................................................................................................... 193
Dynamic ODT Special Use Case ................................................................................................................. 193
Functional Description .............................................................................................................................. 193
Synchronous ODT Mode ................................................................................................................................ 199
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM
Description
ODT Latency and Posted ODT .................................................................................................................... 199
Timing Parameters .................................................................................................................................... 199
ODT Off During READs .............................................................................................................................. 202
Asynchronous ODT Mode .............................................................................................................................. 204
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 206
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 208
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 210
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. K 9/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
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