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HI-506, HI-507, HI-508, HI-509
Data Sheet
October 30, 2007
FN3142.8
Single 16 and 8/Differential 8-Channel and
4-Channel CMOS Analog Multiplexers
The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS
multiplexers each include an array of sixteen and eight
analog switches respectively, a digital decoder circuit for
channel selection, voltage reference for logic thresholds, and
an enable input for device selection when several
multiplexers are present. The Dielectric Isolation (DI)
process used in fabrication of these devices eliminates the
problem of latchup. DI also offers much lower substrate
leakage and parasitic capacitance than conventional junction
isolated CMOS (see Application Note AN520).
The switching threshold for each digital input is established by
an internal +5V reference, providing a guaranteed minimum
2.4V for logic “1” and maximum 0.8V for logic “0”. This allows
direct interface without pullup resistors to signals from most
logic families: CMOS, TTL, DTL and some PMOS. For
protection against transient overvoltage, the digital inputs
include a series 200Ω resistor and diode clamp to each
supply.
The HI-506 is a single 16-channel, the HI-507 is an
8-channel differential, the HI-508 is a single 8-channel and
the HI-509 is a 4-channel differential multiplexer.
If input overvoltages are present, the HI-546/HI-547/HI-548/
HI-549 multiplexers are recommended.
Features
• Pb-Free Available (RoHS Compliant) (See Ordering Info)
• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . . . . 180Ω
• Wide Analog Signal Range
. . . . . . . . . . . . . . . . . . . . .
±15V
• TTL/CMOS Compatible
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V
• Break-Before-Make Switching
• No Latch-Up
• Replaces DG506A/DG506AA and DG507A/DG507AA
• Replaces DG508A/DG508AA and DG509A/DG509AA
• Pb-Free Available (RoHS Compliant)
Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-506, HI-507, HI-508, HI-509
Ordering Information
PART NUMBER
HI1-0506-2
HI1-0506-5
HI4P0506-5
HI4P0506-5Z (Note 1)
HI9P0506-5
HI9P0506-9
HI9P0506-9Z (Note 1)
HI1-0507-2
HI3-0507-5
HI3-0507-5Z
HI1-0508-2
HI1-0508-5
HI3-0508-5
HI3-0508-5Z (Note 1)
HI9P0508-5
HI9P0508-5Z (Notes 1, 2)
HI9P0508-9
HI9P0508-9Z (Note 1)
HI1-0509-2
HI1-0509-4
HI1-0509-5
HI3-0509-5
HI4P0509-5
HI4P0509-5Z (Notes 1, 2)
HI9P0509-5
HI9P0509-5Z (Notes 1, 2)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
PART MARKING
HI1-506-2
HI1-506-5
HI4P 506-5
HI4P 506-5Z
HI9P506-5
HI9P506-9
HI9P506-9Z
HI1-507-2
HI3-507-5
HI3-507-5Z
HI1-508-2
HI1-508
HI3-508-5
HI3-508-5Z
HI9P508-5
HI9P508-5Z
HI9P508-9
HI9P508-9Z
HI1-509-2
HI1-509-4
HI1-509-5
HI3-509-5
HI4P 509-5
HI4P 509-5Z
HI9P 509-5
HI9P 509-5Z
TEMP.
RANGE (°C)
-55 to +125
0 to +75
0 to +75
0 to +75
0 to +75
-40 to +85
-40 to +85
-55 to +125
0 to +75
0 to +75
-55 to 125
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
-40 to +85
-40 to +85
-55 to +125
-25 to +85
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
0 to +75
PACKAGE
28 Ld CERDIP
28 Ld CERDIP
28 Ld PLCC
28 Ld PLCC (Pb-free)
28 Ld SOIC
28 Ld SOIC
28 Ld SOIC (Pb-free)
28 Ld CERDIP
28 Ld PDIP
PKG. DWG. #
F28.6
F28.6
N28.45
N28.45
M28.3
M28.3
M28.3
F28.6
E28.6
28 Ld PDIP (Note 3) (Pb-free) E28.6
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
F16.3
F16.3
E16.3
16 Ld PDIP (Note 3) (Pb-free) E16.3
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
20 Ld PLCC
20 Ld PLCC (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
M16.15
M16.15
M16.15
M16.15
F16.3
F16.3
F16.3
E16.3
N20.35
N20.35
M16.15
M16.15
2
FN3142.8
October 30, 2007
HI-506, HI-507, HI-508, HI-509
Pinouts
HI-506 (CERDIP, SOIC)
TOP VIEW
HI-506 (PLCC)
TOP VIEW
+V
SUPPLY
-V
SUPPLY
27
OUT
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11 9
IN 10 10
IN 9 11
GND 12
NC 13
ADDRESS A
3
14
27 -V
SUPPLY
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDRESS A
0
16 ADDRESS A
1
15 ADDRESS A
2
IN 9
11
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
5
6
7
8
9
10
4
3
2
1
28
IN 8
26
25
24
23
22
21
20
19
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
18
ENABLE
FN3142.8
October 30, 2007
NC
13
NC
12
GND
14
A
3
NC
+V
SUPPLY
1
28 OUT
IN 16
15
A
2
16
A
1
17
A
0
16 A
1
15 A
2
HI-507 (PDIP, CERDIP)
TOP VIEW
+V
SUPPLY
1
OUT B 2
NC 3
IN 8B 4
IN 7B 5
IN 6B 6
IN 5B 7
IN 4B 8
IN 3B 9
IN 2B 10
IN 1B 11
GND 12
NC 13
NC 14
28 OUT A
27 -V
SUPPLY
26 IN 8A
25 IN 7A
24 IN 6A
23 IN 5A
22 IN 4A
21 IN 3A
20 IN 2A
19 IN 1A
18 ENABLE
17 ADDRESS A
0
16 ADDRESS A
1
15 ADDRESS A
2
HI-508 (PDIP, CERDIP, SOIC)
TOP VIEW
A
0
1
ENABLE 2
-V
SUPPLY
3
IN 1 4
IN 2 5
IN 3 6
IN 4 7
OUT 8
14 GND
13 +V
SUPPLY
12 IN 5
11 IN 6
10 IN 7
9 IN 8
3
HI-506, HI-507, HI-508, HI-509
Pinouts
(Continued)
HI-509 (PDIP, CERDIP, SOIC)
TOP VIEW
A
0
1
ENABLE 2
-V
SUPPLY
3
IN 1A 4
IN 2A 5
IN 3A 6
IN 4A 7
OUT A 8
16 A
1
15 GND
14 +V
SUPPLY
13 IN 1B
12 IN 2B
11 IN 3B
10 IN 4B
9 OUT B
NC
IN 2A
IN 3A
6
7
8
9
IN 4A
10
OUT A
11
NC
12
OUT B
13
IN 4B
-V
SUPPLY
IN 1A
4
5
ENABLE
HI-509 (PLCC)
TOP VIEW
3
2
1
20
19
18 +V
SUPPLY
17
IN 1B
16 NC
15 IN 2B
14 IN 3B
4
GND
NC
A
0
A
1
FN3142.8
October 30, 2007
PCB设计
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