Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> RN80532KC049512

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RN80532KC049512: 产品描述Microprocessor, 32-Bit, 2200MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小3MB，共100页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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RN80532KC049512概述

Microprocessor, 32-Bit, 2200MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603

RN80532KC049512规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Intel(英特尔)
零件包装代码	PGA
包装说明	SPGA, PGA603,25X31,50
针数	603
Reach Compliance Code	unknown
ECCN代码	3A001.A.3
地址总线宽度	36
位大小	32
边界扫描	YES
最大时钟频率	100 MHz
外部数据总线宽度	64
格式	FLOATING POINT
集成缓存	YES
JESD-30 代码	S-CPGA-P603
JESD-609代码	e0
长度	53.34 mm
低功率模式	YES
端子数量	603
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	SPGA
封装等效代码	PGA603,25X31,50
封装形状	SQUARE
封装形式	GRID ARRAY, SHRINK PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	1.4,3.3 V
认证状态	Not Qualified
座面最大高度	5.45 mm
速度	2200 MHz
最大压摆率	48100 mA
最大供电电压	1.46 V
最小供电电压	1.352 V
表面贴装	NO
技术	CMOS
端子面层	Tin/Lead (Sn/Pb)
端子形式	PIN/PEG
端子节距	1.27 mm
端子位置	PERPENDICULAR
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	53.34 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR

文档解析

64-bit Intel® Xeon™ Processor with 2 MB L2 Cache 是一款面向企业级应用的处理器，强调可扩展性和可靠性。它支持双处理器工作站和服务器，运行频率从 2.80 GHz 到 3.60 GHz，采用 Intel NetBurst 微架构。该处理器通过 Hyper-Threading Technology 提升多线程性能，并保持对 IA-32 软件的二进制兼容性。适用于多种操作系统平台，包括 Windows XP、Windows Server 2003 和 Linux，为部门级服务器提供高效计算能力。关键架构特性包括 800 MHz 系统总线，支持 Source-Synchronous Transfer，优化数据传输效率；2 MB L2 全速缓存采用 ECC 保护，确保数据完整性。处理器还集成了 Advanced Dynamic Execution 和 Hyper Pipelined Technology，增强指令吞吐量。通过 Intel EM64T，它实现 64 位内存寻址，支持高达 64 GB 物理内存，并包括 SSE2 和 SSE3 指令集以加速浮点运算。安全功能如 Execute Disable Bit 与系统管理特性结合，提升整体防护能力。在功耗控制方面，处理器采用 Demand Based Switching 和 Enhanced Intel SpeedStep® Technology，动态调整电压和频率，适应负载变化。热管理机制如 Thermal Monitor 在高温事件中触发保护，确保系统稳定性。封装设计兼容 mPGA604 插座，支持独立电源供应，便于集成到服务器主板。这些设计使其成为互联网基础设施和高性能计算环境的理想选择，提供持续的高可用性服务。

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64-bit Intel

Xeon™ Processor with 2

MB L2 Cache

Datasheet

Product Features

■

Available at 2.80, 3, 3.20, 3.40, 3.60 GHz

90 nm process technology

Dual processing server/workstation support

Binary compatible with applications

running on previous members of Intel’s IA-

32 microprocessor line

Intel NetBurst

micro-architecture

Hyper-Threading Technology

Hardware support for multithreaded

applications

Fast 800 MHz system bus

Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor

core frequency

Hyper Pipelined Technology

Advanced Dynamic Execution

Very deep out-of-order execution

Enhanced branch prediction

Execute Disable Bit

■

Includes 16-KB Level 1 data cache

Intel

Extended Memory 64 Technology

(Intel

EM64T)

2 MB Advanced Transfer Cache (On-die,

full speed Level 2 (L2) Cache) with 8-way

associativity and Error Correcting Code

(ECC)

Enables system support of up to 64 GB of

physical memory

144 Streaming SIMD Extensions 2 (SSE2)

instructions

13 Streaming SIMD Extensions 3 (SSE3)

instructions

Enhanced floating-point and multimedia

unit for enhanced video, audio, encryption,

and 3D performance

System Management mode

Thermal Monitor

Machine Check Architecture (MCA)

Demand Based Switching (DBS) with

Enhanced Intel SpeedStep

Technology

The 64-bit Intel

Xeon™ processor with 2 MB L2 cache is designed for high-performance dual-

processor workstation and server applications. Based on the Intel NetBurst micro- architecture

and the Hyper-Threading Technology, it is binary compatible with previous Intel Architecture

(IA-32) processors. The 64-bit Intel Xeon processor with 2 MB L2 cache is scalable to two

processors in a multiprocessor system providing exceptional performance for applications

running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*,

and UNIX*.

The 64-bit Intel Xeon processor with 2 MB L2 cache delivers

compute power at unparalleled value and flexibility for powerful

workstations, internet infrastructure, and departmental server

applications. The Intel NetBurst micro-architecture and Hyper-

Threading Technology deliver outstanding performance and

headroom for peak internet server workloads, resulting in faster

response times, support for more users, and improved scalability.

Document Number: 306249-001

February 2005

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

Itanium

2 Processor may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request.

MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled

platforms may require licenses from various entities, including Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Intel, Pentium, Intel Xeon, SpeedStep, Intel NetBurst, Intel Extended Memory 64 Technology, and Itanium are trademarks or registered trademarks of

Intel Corporation or its subsidiaries in the United States and other countries.

Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with a processor, chipset, BIOS, OS, device drivers and

applications enabled for Intel EM64T. Processor will not operate (including 32-bit operation) without an Intel EM64T-enabled BIOS. Performance will

vary depending on your hardware and software configurations. Intel EM64T-enabled OS, BIOS, device drivers and applications may not be available.

Check with your vendor for more information.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Introduction

..................................................................................................................9

1.1

1.2

1.3

Terminology.........................................................................................................10

References .......................................................................................................... 12

State of Data ....................................................................................................... 13

Power and Ground Pins ...................................................................................... 15

Decoupling Guidelines ........................................................................................15

2.2.1 VCC Decoupling .....................................................................................15

2.2.2 VTT Decoupling...................................................................................... 15

2.2.3 Front Side Bus AGTL+ Decoupling ........................................................ 15

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................16

2.3.1 Front Side Bus Frequency Select Signals (BSEL[1:0]) .......................... 16

2.3.2 Phase Lock Loop (PLL) and Filter ..........................................................17

Voltage Identification (VID)..................................................................................18

Reserved Or Unused Pins................................................................................... 20

Front Side Bus Signal Groups............................................................................. 20

GTL+ Asynchronous and AGTL+ Asynchronous Signals ...................................22

Test Access Port (TAP) Connection....................................................................22

Mixing Processors ...............................................................................................23

Absolute Maximum and Minimum Ratings ..........................................................23

Processor DC Specifications...............................................................................24

2.11.1 Flexible Motherboard Guidelines (FMB).................................................24

2.11.2 VCC Overshoot Specification .................................................................28

2.11.3 Die Voltage Validation ............................................................................ 29

Package Mechanical Drawings ...........................................................................34

Processor Component Keepout Zones ............................................................... 37

Package Loading Specifications ......................................................................... 37

Package Handling Guidelines ............................................................................. 38

Package Insertion Specifications ........................................................................38

Processor Mass Specifications ...........................................................................38

Processor Materials............................................................................................. 38

Processor Markings............................................................................................. 39

Processor Pin-Out Coordinates...........................................................................40

Signal Definitions................................................................................................. 43

64-bit Intel® Xeon™ Processor with 2 MB L2 Cache Pin Assignments.............. 53

5.1.1 Pin Listing by Pin Name ......................................................................... 53

5.1.2 Pin Listing by Pin Number ...................................................................... 61

Electrical Specifications

...................................................................................... 15

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

Mechanical Specifications

.................................................................................... 33

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Signal Definitions

..................................................................................................... 43

4.1

5.1

Pin Listing

...................................................................................................................53

Datasheet

Thermal Specifications

......................................................................................... 69

6.1

6.2

Package Thermal Specifications ......................................................................... 69

6.1.1 Thermal Specifications ........................................................................... 69

6.1.2 Thermal Metrology ................................................................................. 73

Processor Thermal Features............................................................................... 73

6.2.1 Thermal Monitor ..................................................................................... 73

6.2.2 Thermal Monitor 2 .................................................................................. 74

6.2.3 On-Demand Mode.................................................................................. 75

6.2.4 PROCHOT# Signal Pin .......................................................................... 76

6.2.5 FORCEPR# Signal Pin .......................................................................... 76

6.2.6 THERMTRIP# Signal Pin ....................................................................... 76

6.2.7 TCONTROL and Fan Speed Reduction................................................. 76

6.2.8 Thermal Diode........................................................................................ 77

Power-On Configuration Options ........................................................................ 79

Clock Control and Low Power States.................................................................. 79

7.2.1 Normal State .......................................................................................... 80

7.2.2 HALT or Enhanced HALT Power Down States...................................... 80

7.2.2.1 HALT Power Down State .......................................................... 80

7.2.2.2 Enhanced HALT Power Down State ......................................... 80

7.2.3 Stop Grant State .................................................................................... 81

7.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant

Snoop State ........................................................................................... 82

7.2.4.1 HALT Snoop State, Stop Grant Snoop State ............................ 82

7.2.4.2 Enhanced HALT Snoop State ................................................... 82

7.2.5 Sleep State............................................................................................. 82

Demand Based Switching (DBS) with Enhanced Intel SpeedStep

Technology83

Introduction ......................................................................................................... 85

Mechanical Specifications ................................................................................... 87

8.2.1 Boxed Processor Heatsink Dimensions (CEK) ...................................... 87

8.2.2 Boxed Processor Heatsink Weight......................................................... 95

8.2.2.1 Thermal Solution Weight ........................................................... 95

8.2.3 Boxed Processor Retention Mechanism and Heatsink Support (CEK).. 95

Electrical Requirements ...................................................................................... 95

8.3.1 Fan Power Supply (Active CEK) ............................................................ 95

8.3.2 Boxed Processor Cooling Requirements ............................................... 97

8.3.2.1 1U Passive CEK Heatsink (1U Form Factor) ............................ 97

8.3.2.2 2U Passive CEK Heatsink (2U and above Form Factor) .......... 97

8.3.2.3 2U+ Active CEK Thermal Solution (2U+ and above Pedestal) . 97

Boxed Processor Contents ................................................................................. 98

Debug Port System Requirements...................................................................... 99

Target System Implementation ........................................................................... 99

9.2.1 System Implementation.......................................................................... 99

Logic Analyzer Interface (LAI) ............................................................................ 99

9.3.1 Mechanical Considerations .................................................................. 100

9.3.2 Electrical Considerations...................................................................... 100

Features

....................................................................................................................... 79

7.1

7.2

7.3

Boxed Processor Specifications

....................................................................... 85

8.1

8.2

8.3

8.4

Debug Tools Specifications

................................................................................. 99

9.1

9.2

9.3

Datasheet

Figures

2-1

2-2

2-3

2-4

3-1

3-2

3-3

3-4

3-5

3-6

3-7

6-1

6-2

6-3

7-1

8-1

8-2

8-3

8-4

8-5

8-6

8-7

8-8

8-9

8-10

8-11

8-12

Phase Lock Loop (PLL) Filter Requirements ...................................................... 17

64-bit Intel

Xeon™ Processor with 2 MB L2 Cache Load Current Vs. Time.....26

VCC Static and Transient Tolerance................................................................... 28

VCC Overshoot Example Waveform................................................................... 29

Processor Package Assembly Sketch.................................................................33

Processor Package Drawing (Sheet 1 of 2) ........................................................ 35

Processor Package Drawing (Sheet 2 of 2) ........................................................ 36

Processor Top-Side Markings (Example)............................................................ 39

Processor Bottom-Side Markings (Example) ...................................................... 39

Processor Pinout Coordinates, Top View............................................................ 40

Processor Pinout Coordinates, Bottom View ...................................................... 41

64-bit Intel

Xeon™ Processor with 2 MB L2 Cache Thermal Profiles

A and B (PRB = 1)...............................................................................................71

Case Temperature (TCASE) Measurement Location ......................................... 73

Demand Based Switching Frequency and Voltage Ordering .............................. 75

Stop Clock State Machine ................................................................................... 81

1U Passive CEK Heatsink................................................................................... 85

2U Passive CEK Heatsink................................................................................... 86

Active CEK Heatsink (Representation Only) .......................................................86

Passive 64-bit Intel

Xeon™ Processor with 2 MB L2 Cache Thermal

Solution (2U and Larger) .....................................................................................87

Top-Side Board Keepout Zones (Part 1)............................................................. 88

Top-Side Board Keepout Zones (Part 2)............................................................. 89

Bottom-Side Board Keepout Zones.....................................................................90

Board Mounting Hole Keepout Zones .................................................................91

Volumetric Height Keep-Ins................................................................................. 92

4-Pin Fan Cable Connector (For Active CEK Heatsink)......................................93

4-Pin Base Board Fan Header (For Active CEK Heatsink) ................................. 94

Fan Cable Connector Pinout for 4-Pin Active CEK Thermal Solution ................. 96

Tables

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

2-10

2-11

2-12

2-13

2-14

Datasheet

Features of the 64-bit Intel

Xeon™ Processor with 2 MB L2 Cache ................. 10

Core Frequency to Front Side Bus Multiplier Configuration ................................16

BSEL[1:0] Frequency Table ................................................................................ 17

Voltage Identification Definition 2, 3 ....................................................................19

Front Side Bus Signal Groups............................................................................. 21

Signal Description Table .....................................................................................22

Signal Reference Voltages..................................................................................22

Absolute Maximum and Minimum Ratings ..........................................................23

Voltage and Current Specifications .....................................................................25

VCC Static and Transient Tolerance................................................................... 27

VCC Overshoot Specifications ............................................................................ 28

BSEL[1:0] and VID[5:0] Signal Group DC Specifications.................................... 29

AGTL+ Signal Group DC Specifications ............................................................. 30

PWRGOOD Input and TAP Signal Group DC Specifications.............................. 30

GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC

RN80532KC049512相似产品对比

	RN80532KC049512	RN80532KC064512	RN80528KC021G0K	RN80532KC033512	RN80532KC072512	RN80532KC041512
描述	Microprocessor, 32-Bit, 2200MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603	Microprocessor, 32-Bit, 2600MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603	Microprocessor, 32-Bit, 1500MHz, CMOS, CPGA603, MICRO, PGA-603	Microprocessor, 32-Bit, 1800MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603	Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603	Microprocessor, 32-Bit, 2000MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603
厂商名称	Intel(英特尔)	Intel(英特尔)	Intel(英特尔)	Intel(英特尔)	Intel(英特尔)	Intel(英特尔)
零件包装代码	PGA	PGA	PGA	PGA	PGA	PGA
包装说明	SPGA, PGA603,25X31,50	SPGA,	SPGA, PGA603,25X31,50	SPGA, PGA603,25X31,50	SPGA,	SPGA, PGA603,25X31,50
针数	603	603	603	603	603	603
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
地址总线宽度	36	36	36	36	36	36
位大小	32	32	32	32	32	32
边界扫描	YES	YES	YES	YES	YES	YES
最大时钟频率	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz
外部数据总线宽度	64	64	64	64	64	64
格式	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
集成缓存	YES	YES	YES	YES	YES	YES
JESD-30 代码	S-CPGA-P603	S-CPGA-P603	S-CPGA-P603	S-CPGA-P603	S-CPGA-P603	S-CPGA-P603
长度	53.34 mm	53.34 mm	53.34 mm	53.34 mm	53.34 mm	53.34 mm
低功率模式	YES	YES	YES	YES	YES	YES
端子数量	603	603	603	603	603	603
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	5.45 mm	5.45 mm	5.733 mm	5.45 mm	5.45 mm	5.45 mm
速度	2200 MHz	2600 MHz	1500 MHz	1800 MHz	2800 MHz	2000 MHz
最大供电电压	1.46 V	1.453 V	1.7 V	1.465 V	1.45 V	1.463 V
最小供电电压	1.352 V	1.339 V	1.545 V	1.361 V	1.335 V	1.357 V
表面贴装	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
端子位置	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
宽度	53.34 mm	53.34 mm	53.34 mm	53.34 mm	53.34 mm	53.34 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
封装等效代码	PGA603,25X31,50	-	PGA603,25X31,50	PGA603,25X31,50	-	PGA603,25X31,50
电源	1.4,3.3 V	-	1.6 V	1.4,3.3 V	-	1.4,3.3 V
最大压摆率	48100 mA	-	44200 mA	42400 mA	-	45300 mA

RN80532KC049512

RN80532KC049512概述

RN80532KC049512规格参数

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