HYB25D256400/800T/AT
256-MBit Double Data Rata SDRAM
Features
CAS Latency and Frequency
CAS Latency
2
2.5
.
Maximum Operating Frequency (MHz)
DDR266A
DDR266B
DDR200
-7
-7.5
-8
133
125
100
143
133
125
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
transitions.
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8
µs
Maximum Average Periodic Refresh
Interval
• 2.5V (SSTL_2 compatible) I/O
• V
DDQ
= 2.5V
±
0.2V / V
DD
= 2.5V
±
0.2V
• TSOP66 package
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a
quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a
2n
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O
pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single
2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the
DDR SDRAM during Reads and by the memory
controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differen-
tial clock (CK and CK; the crossing of CK going
HIGH and CK going LOW is referred to as the posi-
tive edge of CK). Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as
well as to both edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of an Active command, which is then
followed by a Read or Write command. The address
bits registered coincident with the Active command
are used to select the bank and row to be accessed.
The address bits registered coincident with the
Read or Write command are used to select the bank
and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read
or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective band-
width by hiding row precharge and activation time.
An auto refresh mode is provided along with a
power-saving power-down mode. All inputs are
compatible with the JEDEC Standard for SSTL_2.
All outputs are SSTL_2, Class II compatible.
Note:
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
3/01
Page 1 of 72
HYB25D256400/800T/AT
256-Mbit Double Data Rate SDRAM
Input/Output Functional Description
Symbol
CK, CK
Type
Input
Function
Clock:
CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-
chronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh.
Chip Select:
All commands are masked when CS is registered HIGH. CS provides for exter-
nal bank selection on systems with multiple banks. CS is considered part of the command
code. The standard pinout includes one CS pin.
Command Inputs:
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or Pre-
charge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
Data Input/Output:
Data bus.
Data Strobe:
Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
FET control:
Optional. Output during every Read and Write access. Is provided to control
isolation switches on modules. Open drain output. Pullup resistor must be tied to V
DDQ
at sec-
ond level of assembly.
The QFC pin is present on this product version, but all timings parameters related to this pin
are not tested on the final product and are only guaranteed by design.
No Connect:
No internal electrical connection is present.
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
2.5V
±
0.2V.
DQ Ground
Power Supply:
2.5V
±
0.2V.
Ground
SSTL_2 reference voltage:
(V
DDQ
/ 2)
CKE
Input
CS
RAS, CAS, WE
Input
Input
DM
Input
BA0, BA1
Input
A0 - A12
Input
DQ
DQS
Input/Output
Input/Output
QFC
Output
NC
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Page 3 of 72
3/01
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
