DATASHEET
CA3260, CA3260A
4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3260A and CA3260 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA3260 series
circuits are dual versions of the popular CA3160 series.
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA3260 Series circuits operate at supply voltages
ranging from 4V to 16V, or
2V
to
8V
when using split
supplies. The CA3260A offers superior input characteristics
over those of the CA3260.
FN1266
Rev.7.00
Dec 10, 2009
Features
• MOSFET Input Stage provides
- Very High Z
I
= 1.5T (1.5 x 10
12
)
(Typ)
- Very Low I
I
. . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(Or Both) Supply Rails
• Pb-Free Available (RoHS Compliant)
Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• Ideal Interface with Digital CMOS
Ordering Information
PART
NUMBER
CA3260E
CA3260EZ
(Note)
CA3260AE
PART
MARKING
CA3260E
CA3260EZ
CA3260AE
TEMP.
RANGE (°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
8 Ld PDIP
8 Ld PDIP*
(Pb-free)
PKG.
DWG. #
E8.3
E8.3
E8.3
E8.3
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single Supply D/A
Converter)
• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)
• Wien Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
CA3260AEZ 3260AEZ
(Note)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
CA3260, CA3260A
(8 LD PDIP)
TOP VIEW
OUTPUT (A)
INV. INPUT (A)
NON INV. INPUT (A)
V-
1
A
2
3
4
8
V+
OUTPUT (B)
INV. INPUT (B)
NON INV. INPUT (B)
-
+
B
+
7
-
6
5
FN1266 Rev.7.00
Dec 10, 2009
Page 1 of 4
CA3260, CA3260A
Absolute Maximum Ratings
DC Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Thermal Information
Thermal Resistance (Typical, Note 2)
JA
(°C/W)
JC
(°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= +25°C, Typical Values Intended Only for Design Guidance.
TYPICAL VALUES
PARAMETER
Input Resistance
Input Capacitance
Unity Gain Crossover Frequency
Slew Rate
Transient Response
Rise Time
Overshoot
Settling Time (to <0.1, V
IN
= 4V
P-P
)
Input Offset Voltage
Input Offset Current
Input Current
Common Mode Rejection Ratio
Large Signal Voltage Gain
SYMBOL
RI
C
I
f
T
SR
t
r
OS
t
S
V
IO
I
IO
I
I
CMRR
A
OL
TEST CONDITIONS
V
S
=
7.5V
f = 1MHz, V
S
=
7.5V
V
S
=
7.5V
V
S
=
7.5V
C
L
= 25pF, R
L
= 2k A
V
= +1,
V
S
=
7.5V
C
L
= 25pF, R
L
= 2k A
V
= +1,
V
S
=
7.5V
V+ = 5V, V- = 0V
V+ = 5V, V- = 0V
V+ = 5V, V- = 0V
V+ = 5V, V- = 0V
V
O
= 4V
P-P
, R
L
= 20k
V+ = 5V, V- = 0V
V+ = 5V, V- = 0V
V
O
= 5V, R
L
=
V+ = 5V, V- = 0V
V
O
= 2.5V, R
L
=
V+ = 5V, V- = 0V
Power Supply Rejection Ratio
Electrical Specifications
PSRR
V
IO
/V+, V+ = 5V, V- = 0V
CA3260A
1.5
4.3
4
10
0.09
10
1.8
2
0.1
2
70
100
100
0 to 2.5
1
1.2
200
CA3260
1.5
4.3
4
10
0.09
10
1.8
6
0.1
2
60
100
100
0 to 2.5
1
1.2
200
UNITS
T
pF
MHz
V/s
µs
%
s
mV
pA
pA
dB
kV/V
dB
V
mA
mA
µV/V
Common Mode Input Voltage Range
Supply Current
V
ICR
I+
For Each Amplifier at T
A
= +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified.
TEST
CONDITIONS
V
S
=
7.5V
V
S
=
7.5V
V
S
=
7.5V
V
O
= 10V
P-P
,
R
L
= 10k
CA3260A
MIN
-
-
-
50
94
80
TYP
2
0.5
5
320
110
95
MAX
5
20
30
-
-
-
MIN
-
-
-
50
94
70
CA3260
TYP
6
0.5
5
320
110
90
MAX
15
30
50
-
-
-
UNITS
mV
pA
pA
kV/V
dB
dB
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain
SYMBOL
|V
IO
|
|I
IO
|
I
I
A
OL
Common Mode Rejection Ratio
CMRR
FN1266 Rev.7.00
Dec 10, 2009
Page 2 of 4
CA3260, CA3260A
Electrical Specifications
For Each Amplifier at T
A
= +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified.
(Continued)
TEST
CONDITIONS
CA3260A
MIN
0
V
IO
/V+
V+ = 17.5V
R
L
= 10k
R
L
=
-
11
-
14.99
-
V
O
= 0V
V
O
= 15V
R
L
=
-
-
-
V
IO
/T
f = 1kHz
-
-
9
1.2
5
6
120
15.5
3
8.5
-
-
-
-
-
-
-
9
1.2
5
8
120
15.5
3
8.5
-
-
mA
mA
mA
µV/°C
dB
12
12
TYP
-0.5 to
12
32
13.3
0.002
15
0
22
20
MAX
10
150
-
0.01
-
0.01
45
45
MIN
0
-
11
-
14.99
-
12
12
CA3260
TYP
-0.5 to
12
32
13.3
0.002
15
0
22
20
MAX
10
320
-
0.01
-
0.01
45
45
UNITS
V
µV/V
V
V
V
V
mA
mA
PARAMETER
Common Mode Input Voltage
Range
Power Supply Rejection Ratio
Maximum Output Voltage
SYMBOL
V
lCR
PSRR
V
OM
+
V
OM
-
V
OM
+
V
OM
-
Maximum Output Current
I
OM
+ Source
I
OM
- Sink
Total Supply Current
V
O
(Amplifier A) = 7.5V
V
O
(Amplifier B) = 7.5V
V
O
(Amplifier A) = 0V
V
O
(Amplifier B) = 0V
V
O
(Amplifier A) = 0V
V
O
(Amplifier B) = 7.5V
Input Offset Voltage
Temperature Drift
Crosstalk
I+
Schematic Diagram
8 V+
AMPLIFIER A
AMPLIFIER B
Q
11
Q
10
D
2
Q
6
Q
7
Q
9
Q
23
Q
21
Q
20
Q
24
Q
25
D
7
D
3
D
6
D
1
Q
12
Q
14
Q
13
R
3
1k
Q
3
R
1
1k
3
Q
1
Q
2
D
4
R
5
2K
C
1
30pF
Q
5
Q
8
Q
22
R
12
2k
C
2
30pF
Q
19
D
5
Q
16
Q
15
D
8
Q
26
R
10
Q
27
1k
Q
17
R
8
1k
5
R
14
300
Q
28
R
13
200k
R
4
1k
R
11
1k
R
6
200k
R
7
300k
Q
4
R
2
1k
2
1
7
6
Q
18
R
9
1k
4
FN1266 Rev.7.00
Dec 10, 2009
Page 3 of 4
CA3260, CA3260A
Dual-In-Line Plastic Packages (PDIP)
N
INDEX
AREA
E1
1 2 3
N/2
-B-
-A-
D
BASE
PLANE
SEATING
PLANE
D1
B1
B
0.010 (0.25) M
D1
-C-
A2
L
A
C
L
E
E8.3
(JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES
SYMBOL
A
A1
A2
B
B1
C
D
D1
E
E1
e
e
A
e
B
L
N
e
A
e
C
C A B S
C
MILLIMETERS
MIN
-
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
MAX
5.33
-
4.95
0.558
1.77
0.355
10.16
-
8.25
7.11
NOTES
4
4
-
-
8, 10
-
5
5
6
5
-
6
7
4
9
Rev. 0 12/93
MIN
-
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
MAX
0.210
-
0.195
0.022
0.070
0.014
0.400
-
0.325
0.280
e
A
1
e
B
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed 0.010
inch (0.25mm).
6. E and e
A
are measured with the leads constrained to be
perpendicular to datum -C- .
7. e
B
and e
C
are measured at the lead tips with the leads
unconstrained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
0.100 BSC
0.300 BSC
-
0.115
8
0.430
0.150
-
2.54 BSC
7.62 BSC
10.92
3.81
8
2.93
© Copyright Intersil Americas LLC 1998-2009. All Rights Reserved.
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For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
FN1266 Rev.7.00
Dec 10, 2009
Page 4 of 4
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