1Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 banks
MT41J128M8 – 16 Meg x 8 x 8 banks
MT41J64M16 – 8 Meg x 16 x 8 banks
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
DD
= V
DDQ
= 1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS READ latency (CL)
POSTED CAS ADDITIVE latency (AL)
Programmable CAS WRITE latency (CWL) based on
t
CK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Options
1
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 11.5mm) Rev. G
– 78-ball (8mm x 10.5mm) Rev. J
• FBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm) Rev. G
– 96-ball (8mm x 14mm) Rev. J
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
– Industrial (–40°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
256M4
128M8
64M16
JP
DA
JT
TW
-093
-107
-125
-15E
-187E
None
IT
:G / :J
•
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-093
1, 2, 3, 4
-107
1, 2, 3
-125
1, 2
-15E
1
-187E
Notes:
1.
2.
3.
4.
Data Rate (MT/s)
2133
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.09
13.91
13.75
13.5
13.1
13.09
13.91
13.75
13.5
13.1
13.09
13.91
13.75
13.5
13.1
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Page Size
256 Meg x 4
32 Meg x 4 x 8 banks
8K
16K (A[13:0])
8 (BA[2:0])
2K (A[11, 9:0])
1KB
128 Meg x 8
16 Meg x 8 x 8 banks
8K
16K (A[13:0])
8 (BA[2:0])
1K (A[9:0])
1KB
64 Meg x 16
8 Meg x 16 x 8 banks
8K
8K (A[12:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3 Part Numbers
Example Part Number: MT41J256M4DA-107:J
-
MT41J
Configuration
Package
Speed
:
Revision
{
:G / :J Revision
Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
256M4
128M8
64M16
Speed Grade
tCK = 0.098ns, CL = 14
tCK = 1.07ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
Temperature
Commercial
Industrial temperature
None
IT
Package
78-ball 8mm x 11.5mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 8mm x 14mm FBGA
96-ball 8mm x 14mm FBGA
Rev.
G
J
G
J
Mark
JP
DA
JT
TW
-093
-107
-125
-15E
-187E
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com
for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Features
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – I
DD
Specifications and Conditions ........................................................................... 30
Electrical Characteristics – I
DD
Specifications .................................................................................................. 41
Electrical Specifications – DC and AC .............................................................................................................. 44
DC Operating Conditions ........................................................................................................................... 44
Input Operating Conditions ........................................................................................................................ 44
AC Overshoot/Undershoot Specification ..................................................................................................... 48
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 51
Slew Rate Definitions for Differential Input Signals ...................................................................................... 53
ODT Characteristics ....................................................................................................................................... 54
ODT Resistors ............................................................................................................................................ 55
ODT Sensitivity .......................................................................................................................................... 56
ODT Timing Definitions ............................................................................................................................. 56
Output Driver Impedance ............................................................................................................................... 60
34 Ohm Output Driver Impedance .............................................................................................................. 61
34 Ohm Driver ............................................................................................................................................ 62
34 Ohm Output Driver Sensitivity ................................................................................................................ 63
Alternative 40 Ohm Driver .......................................................................................................................... 64
40 Ohm Output Driver Sensitivity ................................................................................................................ 64
Output Characteristics and Operating Conditions ............................................................................................ 66
Reference Output Load ............................................................................................................................... 68
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 69
Slew Rate Definitions for Differential Output Signals .................................................................................... 70
Speed Bin Tables ............................................................................................................................................ 71
Electrical Characteristics and AC Operating Conditions ................................................................................... 76
Command and Address Setup, Hold, and Derating ........................................................................................... 96
Data Setup, Hold, and Derating ...................................................................................................................... 104
Commands – Truth Tables ............................................................................................................................. 113
Commands ................................................................................................................................................... 116
DESELECT ................................................................................................................................................ 116
NO OPERATION ........................................................................................................................................ 116
ZQ CALIBRATION LONG ........................................................................................................................... 116
ZQ CALIBRATION SHORT .......................................................................................................................... 116
ACTIVATE ................................................................................................................................................. 116
READ ........................................................................................................................................................ 116
WRITE ...................................................................................................................................................... 117
PRECHARGE ............................................................................................................................................. 118
REFRESH .................................................................................................................................................. 118
SELF REFRESH .......................................................................................................................................... 119
DLL Disable Mode ..................................................................................................................................... 120
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Features
Input Clock Frequency Change ...................................................................................................................... 124
Write Leveling ............................................................................................................................................... 126
Write Leveling Procedure ........................................................................................................................... 128
Write Leveling Mode Exit Procedure ........................................................................................................... 130
Initialization ................................................................................................................................................. 131
Mode Registers .............................................................................................................................................. 133
Mode Register 0 (MR0) ................................................................................................................................... 134
Burst Length ............................................................................................................................................. 134
Burst Type ................................................................................................................................................. 135
DLL RESET ................................................................................................................................................ 136
Write Recovery .......................................................................................................................................... 136
Precharge Power-Down (Precharge PD) ...................................................................................................... 137
CAS Latency (CL) ....................................................................................................................................... 137
Mode Register 1 (MR1) ................................................................................................................................... 138
DLL Enable/DLL Disable ........................................................................................................................... 138
Output Drive Strength ............................................................................................................................... 139
OUTPUT ENABLE/DISABLE ...................................................................................................................... 139
TDQS Enable ............................................................................................................................................. 139
On-Die Termination .................................................................................................................................. 140
WRITE LEVELING ..................................................................................................................................... 140
POSTED CAS ADDITIVE Latency ................................................................................................................ 140
Mode Register 2 (MR2) ................................................................................................................................... 141
CAS Write Latency (CWL) ........................................................................................................................... 142
AUTO SELF REFRESH (ASR) ....................................................................................................................... 142
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 143
SRT vs. ASR ............................................................................................................................................... 143
DYNAMIC ODT ......................................................................................................................................... 143
Mode Register 3 (MR3) ................................................................................................................................... 144
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144
MPR Functional Description ...................................................................................................................... 145
MPR Register Address Definitions and Bursting Order ................................................................................. 146
MPR Read Predefined Pattern .................................................................................................................... 152
MODE REGISTER SET (MRS) Command ........................................................................................................ 152
ZQ CALIBRATION Operation ......................................................................................................................... 153
ACTIVATE Operation ..................................................................................................................................... 154
READ Operation ............................................................................................................................................ 156
WRITE Operation .......................................................................................................................................... 167
DQ Input Timing ....................................................................................................................................... 175
PRECHARGE Operation ................................................................................................................................. 177
SELF REFRESH Operation .............................................................................................................................. 177
Extended Temperature Usage ........................................................................................................................ 179
Power-Down Mode ........................................................................................................................................ 180
RESET Operation ........................................................................................................................................... 188
On-Die Termination (ODT) ............................................................................................................................ 190
Functional Representation of ODT ............................................................................................................. 190
Nominal ODT ............................................................................................................................................ 190
Dynamic ODT ............................................................................................................................................... 192
Dynamic ODT Special Use Case ................................................................................................................. 192
Functional Description .............................................................................................................................. 192
Synchronous ODT Mode ................................................................................................................................ 198
ODT Latency and Posted ODT .................................................................................................................... 198
Timing Parameters .................................................................................................................................... 198
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR3 SDRAM
Features
ODT Off During READs .............................................................................................................................. 201
Asynchronous ODT Mode .............................................................................................................................. 203
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 205
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 207
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 209
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2006 Micron Technology, Inc. All rights reserved.
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