Advanced
CAT25CXXX
Supervisory Circuits with SPI Serial E
2
PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s
10 MHz SPI Compatible
s
1.8 to 6.0 Volt Operation
s
Hardware and Software Protection
s
Zero Standby Current
s
Low Power CMOS Technology
s
SPI Modes (0,0 &1,1)
s
Commercial, Industrial and Automotive
s
Watchdog Timer on
CS
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
Self-Timed Write Cycle
s
8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
s
Page Write Buffer
s
Block Write Protection
Temperature Ranges
s
Active High or Low Reset Outputs
– Protect 1/4, 1/2 or all of E
2
PROM Array
s
Programmable Watchdog Timer
s
Built-in inadvertent Write Protection
– Precision Power Supply Voltage Monitoring
– 5V, 3.3V, 3V and 1.8V Options
– V
CC
Lock Out
DESCRIPTION
The CAT25CXXX is a single chip solution to three
popular functions of EEPROM Memory, precision reset
controller and watchdog timer. The EEPROM Memory is
a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E
2
PROM
internally organized as 256x8/512x8/1024x8/2048x8/
4096x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
2K/4K devices feature a 16-byte page write buffer. The
8K/16K/32K devices feature a 32-byte page write
buffer.The device operates via the SPI bus serial inter-
face and is enabled though a Chip Select (CS). In
addition to the Chip Select, the clock input (SCK), data
in (SI) and data out (SO) are required to access the
device. The reset function of the 25CXXX protects the
system during brown out and power up/down condtions.
During system failure the watchdog timer feature pro-
tects the microcontroller with a reset signal. The
CAT25CXXX is designed with software and hardware
write protection features including Block Lock protec-
tion. The device is available in 8-pin DIP, 8-pin SOIC, 16-
pin SOIC and 14-pin TSSOP packages.
PIN CONFIGURATION
TSSOP Package (U14)
CS
SO
NC
NC
NC
WP
V
SS
SOIC Package (S16)
CS
SO
NC
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
RESET/RESET
NC
NC
NC
NC
SCK
SI
SOIC Package (S)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
RESET/RESET
SCK
SI
DIP Package (P)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
RESET/RESET
SCK
SI
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
RESET/RESET
NC
NC
NC
SCK
SI
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9-95
CAT25CXXX
Advanced
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
RESET/RESET
NC
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Reset I/O
No Connect
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
SO
SI
CS
WP
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
E
2
PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
Reset Controller
High Precision
Watchdog V
CC Monitor
25CXXX F02.1
RESET/RESET
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
(1)
(2)
(3)
(4)
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
This parameter is tested initially and after a design or process change that affects the parameter.
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
This parameter is tested initially and after a design or process change that affects the parameter.
Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Stock No. 21085-01 4/98
9-96
Advanced
CAT25CXXX
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Limits
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL(3)
V
IH(3)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
5
0.4
0
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
4.5V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
9-97
Stock No. 21085-01 4/98
CAT25CXXX
Advanced
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
V
V
OH
t
HO
t
DIS
HI-Z
SO
V
OL
HI-Z
A.C. CHARACTERISTICS
Limits
1.8, 2.5
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
HOLD Time
Write Cycle Time
Output Valid from Clock Low
Output HOLD Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
HOLD Time
250
250
250
0
250
100
100
100
100
100
100
10
200
0
75
50
Min.
50
50
200
200
DC
2
50
2
2
40
40
5
80
Max.
4.5V-5.5V
Min.
10
20
40
40
DC
10
50
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
C
L
= 100pF
C
L
= 50pF
Test
UNITS Conditions
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Stock No. 21085-01 4/98
9-98
Advanced
CAT25CXXX
RESET
RESET/RESET
RESET I/O
RESET:
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins the
device will initiate and maintain a reset condition. RE-
SET pin must be connected through a pull-down and
RESET
pin must be connected through a pull-up device.
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25CXXX
and
CS
high disables the CAT25CXXX.
CS
high takes
the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway) The CAT25CXXX draws ZERO
current in the Standby mode. A high to low transition on
CS
is required prior to any sequence being initiated. A
low to high transition on
CS
after a valid write sequence
is what initiates an internal write cycle.
FUNCTIONAL DESCRIPTION
The CAT25CXXX supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25CXXX to interface directly
with many of today’s popular microcontrollers. The
CAT25CXXX contains an 8-bit instruction register. (The
instruction set and the operation codes are detailed in
the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25CXXX. Input data is latched on the rising edge of the
serial clock.
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25CXXX. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25CXXX. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0.
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X=O for 25C02X/08X/16X/32X. X=A8 for 25C04X
STATUS REGISTER
7
WPEN
6
X
5
WD1
4
WD0
3
BP1
2
BP0
1
WEL
0
RDY
9-99
Stock No. 21085-01 4/98
FPGA/CPLD
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