D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
D
D
D
D
D
D
D
D
D
D
Organization:
DRAM: 262 144 Words
×
16 Bits
SAM: 256 Words
×
16 Bits
Single 5.0-V Power Supply (±10%)
Dual-Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
Serial-Address Memory (SAM) Ports
Write-Per-Bit Function for Selective Write to
Each I/O of the DRAM Port
Byte Write Function for Selective Write to
Lower Byte (DQ0 – DQ7) or Upper Byte
(DQ8– DQ15) of the DRAM Port
4 - Column or 8 - Column Block - Write
Function for Fast Area - Fill Operations
Enhanced Page Mode for Faster Access
With Extended-Data-Output (EDO) Option
for Faster System Cycle Time
CAS-Before-RAS (CBR) and Hidden
Refresh Functions
Long Refresh Period – Every 8 ms
(Maximum)
Full - Register- Transfer Function Transfers
Data from the DRAM to the Serial Register
D
D
D
D
D
D
D
D
D
Split-Register-Transfer Function Transfers
Data from the DRAM to One-Half of the
Serial Register While the Other Half is
Outputing Data to the SAM Port
256 Selectable Serial Register Starting
Points
Programmable Split-Register Stop Point
Up to 55-MHz Uninterrupted Serial-Data
Streams
3-State Serial Outputs for Easy Multiplexing
of Video Data Streams
All Inputs/Outputs and Clocks TTL
Compatible
Compatible With JEDEC Standards
Designed to Work With the Texas
Instruments (TI) Graphics Family
Fabricated Using TI’s Enhanced
Performance Implanted CMOS (EPIC)
Process
performance ranges
ACCESS TIME
ROW ENABLE
tRAC
(MAX)
– 60 Speed
– 70 Speed
60 ns
70 ns
ACCESS TIME
SERIAL DATA
tSCA
(MIN)
15 ns
20 ns
DRAM PAGE
CYCLE TIME
tPC
(MIN)
35 ns
40 ns
DRAM EDO
CYCLE TIME
tPC
(MIN)
30 ns
30 ns
SERIAL
CYCLE TIME
tSCC
(MIN)
18 ns
22 ns
OPERATING CURRENT
SERIAL PORT STANDBY
lCC1
(MAX)
180 mA
165 mA
Table 1. Device Option Table
DEVICE
55165
55166
55175
55176
POWER SUPPLY VOLTAGE
5.0 V
±
0.5 V
5.0 V
±
0.5 V
5.0 V
±
0.5 V
5.0 V
±
0.5 V
BLOCK-WRITE CAPABILITY
4 -column
4 -column
8 - column
8 - column
PAGE / EDO OPERATION
Page
EDO
Page
EDO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1995, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
1
TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
DGH PACKAGE
(TOP VIEW)
VCC
TRG
VSS
SQ0
DQ0
SQ1
DQ1
VCC
SQ2
DQ2
SQ3
DQ3
VSS
SQ4
DQ4
SQ5
DQ5
VCC
SQ6
DQ6
SQ7
DQ7
VSS
WEL
WEU
RAS
A8
A7
A6
A5
A4
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SC
SE
VSS
SQ15
DQ15
SQ14
DQ14
VCC
SQ13
DQ13
SQ12
DQ12
VSS
SQ11
DQ11
SQ10
DQ10
VCC
SQ9
DQ9
SQ8
DQ8
VSS
DSF
NC / GND
CAS
QSF
A0
A1
A2
A3
VSS
PIN NOMENCLATURE
A0 – A8
RAS
CAS
DSF
TRG
WEL, WEU
DQ0 – DQ15
SC
SE
SQ0 – SQ15
QSF
VCC
VSS
NC/GND
Address Inputs
Row-Address Strobe
Column-Address Strobe
Special Function Select
Output Enable, Transfer Select
Write Enable, Byte Select, Write Mask Select
DRAM Data I / O
Serial Clock
Serial Enable
Serial Data Output
Special Function Output
Power Supply
Ground
No Connect / Ground
(Important: not connected internally to VSS)
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
description
The TMS551xx multiport video RAMs are high-speed dual-ported memory devices. Each consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a serial-data register
[serial-access memory (SAM)] organized as 256 words of 16 bits each. These devices support three basic types
of operation: random access to and from the DRAM, serial access from the serial register, and transfer of data
from the DRAM to the SAM. Except during transfer operations, these devices can be accessed simultaneously
and asynchronously from the DRAM and SAM ports.
The TMS551xx multiport video RAMs provide several functions designed to provide higher system-level
bandwidth and to simplify design integration on both the DRAM and SAM ports (see Table 2). On the DRAM
port, greater pixel draw rates are achieved by the block-write function. The TMS5516x devices’ 4-column
block-write function allows 16 bits of data (present in an on-chip color-data register) to be written to any
combination of four adjacent column-address locations, up to a total of 64 bits of data per CAS cycle time.
Similarly, the TMS5517x devices’ 8-column block-write function allows 16 bits of data to be written to any
combination of eight adjacent column-address locations, up to a total of 128 bits of data per CAS cycle time.
Also on the DRAM port, the write-per-bit (or write mask) function allows masking of any combination of the 16
DQs on any write cycle. The persistent write-per-bit function uses a mask register that, once loaded, can be used
on subsequent write cycles without reloading. All TMS551xx devices offer byte control. Byte control can be
applied in write cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The
TMS551xx devices offer enhanced page-mode operation that results in faster access time. The TMS551x6
devices also offer extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and
the standard DRAM cycles.
The TMS551xx devices offer a split-register-transfer (DRAM to SAM) function. This feature enables real-time
register load implementation for continuous serial-data streams without critical timing requirements. The serial
register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half
can be loaded from the DRAM. For applications not requiring real-time register load (for example, loads done
during CRT-retrace periods), the full-register-transfer operation is retained to simplify system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 55 MHz. A separate output, QSF, is included to indicate which half of the serial register is active. Refreshing
the SAM is not required because the data register that comprises the SAM is static.
All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address
lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow
greater system flexibility.
All TMS551xx employ TI’s state-of-the-art EPIC scaled-CMOS, double-level polysilicon/polycide gate
technology combining very high performance with improved reliability.
All TMS551xx are offered in a 64-pin small-outline gull-wing-leaded package (DGH suffix) for direct surface
mounting.
The TMS551xx video RAMs and other TI multiport video RAMs are supported by a broad line of graphics
processors and control devices from Texas Instruments.
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
3
TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
SMVS463 – DECEMBER 1995
4-column functional block diagram (TMS5516x)
DSF
Input
Buffer
1 of 4 Sub-Blocks
(see next page)
Special-
Function
Logic
Refresh
Counter
Input
Buffer
1 of 4 Sub-Blocks
(see next page)
Row
Buffer
9
DQ0 –
DQ15
16
A0 – A8
Output
Buffer
Column
Buffer
1 of 4 Sub-Blocks
(see next page)
Serial-
Address
Counter
Split-
Register
Status
SC
SQ0 – SQ15
16
Serial-
Output
Buffer
QSF
SE
RAS
CAS
TRG
WEx
Timing
Generator
1 of 4 Sub-Blocks
(see next page)
SE
4
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
