FlashFlex51 MCU
SST89E51RC / SST89E52RC / SST89E54RC
SST89V51RC / SST89V52RC / SST89V54RC
SST89E/VE5xRC FlashFlex51 MCU
Preliminary Specifications
FEATURES:
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-for-Pin Package Compatible
• SST89E5xRC Operation
– 0 to 40 MHz at 5V
• SST89V5xRC Operation
– 0 to 33 MHz at 3V
• Total 512 Byte Internal RAM
(256 Byte by default +
256 Byte enabled by software)
• Single Block SuperFlash EEPROM
– SST89E/V54RC: 16 KByte primary partition +
1 KByte secondary partition
– SST89E/V52RC: 8 KByte primary partition +
1 KByte secondary partition
– SST89E/V51RC: 4 KByte primary partition +
1 KByte secondary partition
– Primary Partition is divided into Four Pages
– Secondary Partition has One Page
– Individual Page Security Lock
– In-System Programming (ISP)
– In-Application Programming (IAP)
– Small-Sector Architecture: 128-Byte Sector Size
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Port 1 pins (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing error detection
– Automatic address recognition
• Eight Interrupt Sources at 4 Priority Levels
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins)
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• Selectable Operation Clock
– Divide down to 1/4, 1/16, 1/256, or 1/1024th
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 44-lead PLCC
– 44-lead TQFP
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E/V54RC, SST89E/V52RC, and SST89E/
V51RC are members of the FlashFlex51 family of 8-bit
microcontroller products designed and manufactured with
SST’s patented and proprietary SuperFlash CMOS semi-
conductor process technology. The split-gate cell design
and thick-oxide tunneling injector offer significant cost and
reliability benefits for our customers.The devices use the
8051 instruction set and are pin-for-pin compatible with stan-
dard 8051 microcontroller devices.
The device comes with 17/9/5 KByte of on-chip flash
EEPROM program memory which is divided into 2 inde-
pendent program memory partitions. The primary partition
occupies 16/8/4 KByte of internal program memory space
and the secondary partition occupies 1 KByte of internal
program memory space.
The flash memory can be programmed via a standard
87C5x OTP EPROM programmer fitted with a special
adapter and firmware for SST’s devices. During power-on
©2005 Silicon Storage Technology, Inc.
S71259(01)-00-000
2/05
1
reset, the devices can be configured as either a slave to an
external host for source code storage or a master to an
external host for an in-system programming (ISP) opera-
tion. The devices are designed to be programmed in-sys-
tem on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of the boot-
strap loader in memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via
an ISP operation. A sample bootstrap loader is available for
the user’s reference and convenience only; SST does not
guarantee its functionality or usefulness. Chip-Erase opera-
tions will erase the pre-programmed sample code.
In addition to 17/9/5 KByte of SuperFlash EEPROM pro-
gram memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 512 x8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
FlashFlex51 MCU
SST89E51RC / SST89E52RC / SST89E54RC
SST89V51RC / SST89V52RC / SST89V54RC
Preliminary Specifications
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
1.0 FUNCTIONAL BLOCKS
F
UNCTIONAL
B
LOCK
D
IAGRAM
8051
CPU Core
ALU,
ACC,
B-Register,
Instruction Register,
Program Counter,
Timing and Control
Oscillator
Interrupt
Control
8 Interrupts
Watchdog Timer
Flash Control Unit
SuperFlash
EEPROM
Primary
Partition
4K/8K/16K x8
1
Secondary
Partition
1K x8
RAM
512 x8
8
I/O Port 0
8
Security
Lock
I/O Port 1
8
I/O Port 2
I/O
8
I/O Port 3
I/O
I/O
I/O
Timer 0 (16-bit)
Timer 1 (16-bit)
SPI
Timer 2 (16-bit)
8-bit
Enhanced
UART
1259 B1.1
PCA
1. 16K x8 for SST89E/V54RC
8K x8 for SST89E/V52RC
4K x8 for SST89E/V51RC
©2005 Silicon Storage Technology, Inc.
S71259(01)-00-000
2/05
2
FlashFlex51 MCU
SST89E51RC / SST89E52RC / SST89E54RC
SST89V51RC / SST89V52RC / SST89V54RC
Preliminary Specifications
2.0 PIN ASSIGNMENTS
P1.4 (SS# / CEX1)
P1.1 (T2 EX)
P1.3 (CEX0)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
44 43 42 41 40 39 38 37 36 35 34
(CEX2 / MOSI) P1.5
(CEX3 / MISO) P1.6
(CEX4 / SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
(T1) P3.5
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
NC
ALE/PROG#
PSEN#
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
44-lead TQFP
Top View
11
23
12 13 14 15 16 17 18 19 20 21 22
(A11) P2.3
(WR#) P3.6
(RD#) P3.7
(A10) P2.2
(A12) P2.4
NC
(A8) P2.0
(A9) P2.1
XTAL2
XTAL1
VSS
P0.3 (AD3)
1259 44-tqfp TQJ P2.0
P1.2 (ECI)
P1.0 (T2)
FIGURE
2-1: P
IN
A
SSIGNMENTS FOR
44-
LEAD
TQFP
P1.4 (SS# / CEX1)
P1.1 (T2 EX)
P1.3 (CEX0)
VDD
NC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
6
(CEX2 / MOSI) P1.5
(CEX3 / MISO) P1.6
(CEX4 / SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
(T1) P3.5
7
8
9
10
11
12
13
14
15
16
5
4
3
2 1 44 43 42 41 40
39
38
37
36
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
NC
ALE/PROG#
PSEN#
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
44-lead PLCC
Top View
17
29
18 19 20 21 22 23 24 25 26 27 28
(WR#) P3.6
(RD#) P3.7
XTAL2
XTAL1
V
SS
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
P0.3 (AD3)
35
34
33
32
31
30
1259 44-plcc NJ P3.0
P1.2 (ECI)
P1.0 (T2)
FIGURE
2-2: P
IN
A
SSIGNMENTS FOR
44-
LEAD
PLCC
S71259(01)-00-000
2/05
©2005 Silicon Storage Technology, Inc.
3
V
DD
NC
FlashFlex51 MCU
SST89E51RC / SST89E52RC / SST89E54RC
SST89V51RC / SST89V52RC / SST89V54RC
Preliminary Specifications
2.1 Pin Descriptions
TABLE
Symbol
P0[7:0]
2-1: P
IN
D
ESCRIPTIONS
(1
OF
2)
Type
1
I/O
Name and Functions
Port 0:
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can
sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in this state
can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external code and data memory. In this application, it uses
strong internal pull-ups when transitioning to ‘1’s. Port 0 also receives the code bytes during
the external host mode programming, and outputs the code bytes during the external host
mode verification. External pull-ups are required during program verification or as a general
purpose I/O port.
P1[7:0]
I/O with internal
Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
pull-up
can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when ‘1’s are writ-
ten to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups. P1[5, 6, 7] have high current
drive of 16 mA. Port 1 also receives the low-order address byte during the external host mode
programming and verification.
I/O
I
I
I/O
T2:
External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2
T2EX:
Timer/Counter 2 capture/reload trigger and direction control
ECI:
External Clock Input
This signal is the external clock input for the PCA.
CEX0:
Capture/Compare External I/O for PCA Module 0
Each capture/compare module connects to a Port 1 pin for external I/O.
When not used by the PCA, this pin can handle standard I/O.
SS#:
Slave port select input for SPI
OR
CEX1:
Capture/Compare External I/O for PCA Module 1
MOSI:
Master Output line, Slave Input line for SPI
OR
CEX2:
Capture/Compare External I/O for PCA Module 2
MISO:
Master Input line, Slave Output line for SPI
OR
CEX3:
Capture/Compare External I/O for PCA Module 3
SCK:
Master clock output, slave clock input line for SPI
OR
CEX4:
Capture/Compare External I/O for PCA Module 4
Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled
high by the internal pull-ups when ‘1’s are written to them and can be used as inputs in this
state. As inputs, Port 2 pins that are externally pulled low will source current because of the
internal pull-ups. Port 2 sends the high-order address byte during fetches from external pro-
gram memory and during accesses to external Data Memory that use 16-bit address
(MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to ‘1’s.
Port 2 also receives the high-order address byte during the external host mode programming
and verification.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when ‘1’s are writ-
ten to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also receives the high-
order address byte during the external host mode programming and verification.
RXD:
Universal Asynchronous Receiver/Transmitter (UART) - Receive input
TXD:
UART - Transmit output
INT0#:
External Interrupt 0 Input
S71259(01)-00-000
2/05
P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
I/O
P1[5]
I/O
P1[6]
I/O
P1[7]
I/O
P2[7:0]
I/O
with internal
pull-up
P3[7:0]
I/O
with internal
pull-up
P3[0]
P3[1]
P3[2]
I
O
I
©2005 Silicon Storage Technology, Inc.
4
FlashFlex51 MCU
SST89E51RC / SST89E52RC / SST89E54RC
SST89V51RC / SST89V52RC / SST89V54RC
Preliminary Specifications
TABLE
Symbol
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
PSEN#
2-1: P
IN
D
ESCRIPTIONS
(C
ONTINUED
) (2
OF
2)
Type
1
I
I
I
O
O
I/O
Name and Functions
INT1#:
External Interrupt 1 Input
T0:
External count input to Timer/Counter 0
T1:
External count input to Timer/Counter 1
WR#:
External Data Memory Write strobe
RD#:
External Data Memory Read strobe
Program Store Enable:
PSEN# is the Read strobe to external program. When the device is
executing from internal program memory, PSEN# is inactive (High). When the device is exe-
cuting code from external program memory, PSEN# is activated twice each machine cycle,
except that two PSEN# activations are skipped during each access to external data memory.
A forced high-to-low input transition on the PSEN# pin while the RST input is continually held
high for more than 10 machine cycles will cause the device to enter external host mode pro-
gramming.
Reset:
While the oscillator is running, a “high” logic state on this pin for two machine cycles
will reset the device. If the PSEN# pin is driven by a high-to-low input transition while the RST
input pin is held “high,” the device will enter the external host mode, otherwise the device will
enter the normal operation mode.
External Access Enable:
EA# must be connected to V
SS
in order to enable the device to
fetch code from the external program memory. EA# must be strapped to V
DD
for internal pro-
gram execution. However, Disable-Extern-Boot will disable EA#, and program execution is
only possible from internal program memory. The EA# pin can tolerate a high voltage
2
of 12V.
Address Latch Enable:
ALE is the output signal for latching the low byte of the address dur-
ing an access to external memory. This pin is also the programming pulse input (PROG#) for
flash programming. Normally the ALE
3
is emitted at a constant rate of 1/6 the crystal fre-
quency
4
and can be used for external timing and clocking. One ALE pulse is skipped during
each access to external data memory. However, if AO is set to 1, ALE is disabled.
No Connect
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
Power Supply
Ground
T2-1.0 1259
RST
I
EA#
I
ALE/PROG#
I/O
NC
XTAL1
XTAL2
V
DD
V
SS
I/O
I
O
I
I
1. I = Input; O = Output
2. It is not necessary to receive a 12V programming supply voltage during flash programming.
3.ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes
other than normal working mode. The solution is to add a pull-up resistor of 3-50 KΩ to V
DD
, e.g. for ALE pin.
4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency.
©2005 Silicon Storage Technology, Inc.
S71259(01)-00-000
2/05
5
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