UT54ACS164646S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver
Advanced Datasheet
May 17, 2006
www.aeroflex.com/radhard
FEATURES
Voltage translation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
Independent registers for A and B buses
Multiplexed real-time and stored data
Flow-through architecture optimizes PCB layout
Cold- and Warm-sparing
- 1MΩ minimum input impedance power-off
- Guranteed output tri-state while one power supply is "off"
and the other is "on"
Schmitt trigger inputs to filter noisy signals
0.6µm
Commercial RadHard
TM
CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET >40 MeV-cm
2
/mg
High speed, low power consumption
Available QML Q or V processes
Standard Microcircuit Drawing: 5962-06234
Package:
- 56-pin ceramic flatpack
DESCRIPTION
The UT54ACS164646S is a 16-bit, MultiPurpose, registered,
level shifting, bus transceiver consisting of D-type flip-flops,
control circuitry, and 3-state outputs arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. The high-speed, low power
UT54ACS164646S transceiver is designed to perform multi-
ple functions including: asynchronous two-way communica-
tion, signal buffering, voltage translation, cold- and warm-
sparing. The device can be used as two independant 8-bit
transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the
appropriate clock (CLKAB or CLKBA) input. With either
V
DD
supply equal to zero volts, the UT54ACS164646S out-
puts and inputs present a minimum impedance of 1MΩ mak-
ing it ideal for “cold-spare” and "warm-spare" applications. By
virtue of its flexible power supply interface, the
UT54ACS164646S may operate as a 3.3-volt only, 5-volt only,
or mixed 3.3V/5V bus transceiver.
Pin Names
OEx
DIRx
xAx
xBx
xSAB
xSBA
xCLKAB
xCLKBA
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side B Inputs or 3-State Outputs (5V Port)
Select real-time or stored A bus data to B bus
Store A bus data
Store B bus data
IN
D
Select real-time or stored B bus data to A bus
EV
Side A Inputs or 3-State Outputs (3.3V Port)
EL
1
O
PIN DESCRIPTION
PM
The Output-enable (OEx) and direction-control (DIRx) inputs
are provided to control the tri-state function and input/output
direction of the transceiver respectively. The select controls
(SAB and SBA) select whether stored register data or real-time
data is driven to the outputs as determined by the DIRx inputs.
The circuitry used for select control eliminates the typical
decoding glitch that occurs in a multiplexer during the transi-
tion between stored and real-time data. Regardless of the
selected operating mode ("real-time" or "recall"), a rising edge
on the port input clocks (xCLKAB and xCLKBA) will latch
the corresponding I/O states into their respective registers.
Furthermore, when a data port is isolated (OEx = high), A-port
data may be stored into its corrsponding register while B-port
data may be independantly stored into its corresponding regis-
ters. Therefore, when an output function is disabled, the input
function is still enabled and may be used to store and transmit
data. Lastly, only one of the two buses, xA-port or xB-port,
may be driven at a time.
EN
T
POWER TABLE
Port B
5 Volts
5 Volts
3.3 Volts
V
SS
V
SS
3.3V or 5V
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
V
SS
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port B Warm Spare
Port A Warm Spare
I/O GUIDELINES
Control signals DIRx, OEx, xSAB, xSBA, xCLKAB, and
xCLKBA are 5-volt tolerant inputs power by V
DDA
. Therefore,
when V
DDA
is at 3.3-volts, either 3.3- or 5-volt CMOS logic
levels may be applied to all control inputs. Additionally, it is
recommended that all unused inputs be tied to V
SS
through a
1KΩ resistor. Input signal transistion should be driven to the
UT54ACS164646S with a rise and fall time that is < 100µs.
POWER APPLICATION GUIDELINES
For proper operation connect power to all V
DDx
and ground all
V
SS
pins (i.e., no floating V
DDx
or V
SS
input pins). By virtue of
the UT54ACS164646S warm-spare feature, power supplies
V
DDB
and V
DDA
may be applied to the device in any order. To
ensure the device is in cold-spare, both supplies, V
DDB
and
V
DDA
, must be equal to V
SS
+/- 0.3V. Warm-spare operation
is in effect when on power supply is >1V and the other power
supply is equal to V
SS
+/- 0.3V. If V
DDB
has a power-on ramp
rate longer than 1 second, then V
DDA
should be powered-on
first to ensure proper control of DIRx and OEx. During normal
operation of the part, after power-up, ensure V
DDB
> V
DDA
.
FUNCTION TABLE
Inputs
OEx
X
X
H
H
L
L
L
L
+
DIRx
X
X
X
X
L
L
H
H
xCLKAB
↑
X
↑
H or L
X
X
X
H or L
xCLKBA
X
↑
↑
H or L
X
H or L
X
X
xSAB
X
X
X
X
X
X
L
H
xSBA
X
X
X
X
L
H
X
Data I/O
+
xA1-xA8
Input
Unspecified
Input
Input
Output
Output
xB1-xB8
Unspecified
PM
Input
Input
Input
Input
Input
Output
Output
O
3
EL
Input
X
Input
The data-output functions may be enabled or disabled by various signals OEx or DIRx. Data-input functions are always enabled, i.e. data at the bus terminals is
stored on every low-to-high transition of the clock inputs.
IN
D
EV
EN
Store A, B unspecified
+
Store B, A unspecified
+
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Recall stored B data to A bus
Real-time A data to B Bus
Recall stored A data to B bus
T
Operation or Function
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL LET Threshold
SEU Onset LET Threshold
SEU Error Rate
2
Neutron Fluence
3
Dose Rate Survivability
Dose Rate Upset
LIMIT
1.0E5
>111
TBD
TBD
1.0E14
TBD
TBD
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
errors/bit-day
n/cm
2
rads(Si)/sec
rads(Si)/sec
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Adams 90% worst case particle environment, geosynchronous orbit, 100mils of Aluminum shielding
3. Not tested, inherent of CMOS technology.
WEIBUL PARAMETERS
SHAPE
PARAMETER
TBD
WIDTH
PARAMETER
TBD
SATURATED
CROSS-SECTION
TBD
ONSET
LET
TBD
DEVICE
DEPTH
TBD
FUNNEL
DEPTH
TBD
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/OB
(Port B)
2
V
I/OA
(Port A)
2
V
DDB
V
DDA
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin
Voltage any pin
Supply voltage
Supply voltage
EN
PM
O
+175
20
±10
1
5
LIMIT (Mil only)
-0.3 to V
DDB
+0.3
-0.3 to V
DDA
+0.3
-0.3 to 6.0
-0.3 to 6.0
-65 to +150
T
UNITS
V
V
V
V
°C
°C
°C/W
mA
W
Storage Temperature range
Thermal resistance junction to case
DC input current
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (V
DDx
= V
SS
+/- 0.3V), V
I/Ox
may be -0.3V to the maximum recommended operating V
DDx
+ 0.3V.
IN
D
Maximum power dissipation
EV
Maximum junction temperature
EL
能源基础设施
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