Si5335
W
EB
-C
USTOMIZABLE
, A
NY
- F
REQUENCY
, A
NY
- O
U TP U T
Q
UAD
C
LOCK
G
ENERATOR
/B
U FF E R
Features
CLK0A
CLK0B
VDD
VDDO0
20
RSVD_GND
Low power MultiSynth™ technology
enables independent, any-frequency
synthesis of four frequencies
Configurable as a clock generator or
clock buffer device
Three independent, user-assignable,
pin-selectable device configurations
Highly-configurable output drivers with
up to four differential outputs, eight
single-ended clock outputs, or a
combination of both
Low phase jitter of 0.7 ps RMS
Flexible input reference:
External crystal: 25 or 27 MHz
CMOS input: 10 to 200 MHz
SSTL/HSTL input: 10 to 350 MHz
Differential input: 10 to 350 MHz
Independently configurable outputs
support any frequency or format:
LVPECL/LVDS/CML: 1 to 350 MHz
HCSL: 1 to 250 MHz
CMOS: 1 to 200 MHz
SSTL/HSTL: 1 to 350 MHz
Independent output voltage per driver:
1.5, 1.8, 2.5, or 3.3 V
Single supply core with excellent
PSRR: 1.8, 2.5, 3.3 V
Up to five user-assignable pin
functions simplify system design:
SSENB (spread spectrum control),
RESET, Master OEB or OEB per pin,
and Frequency plan select
(FS1, FS0)
Loss of signal alarm
PCIe-compliant spread spectrum
clocking (SSC):
100 MHz
0.5% down spread
31.5 kHz modulation rate
Two selectable loop bandwidth
settings: 1.6 MHz or 475 kHz
Easy to customize with web-based
utility
Small size: 4 x 4 mm, 24-QFN
Low power (core):
45 mA (PLL mode)
12 mA (Buffer mode)
Wide temperature range: –40 to
+85 °C
Ordering Information:
See page 41.
Pin Assignments
Top View
24
23
22
21
19
18
CLK1A
17
CLK1B
16
VDDO1
15
VDDO2
14
CLK2A
13
CLK2B
XA/CLKIN
1
XB/CLKINB
2
P3
3
GND
4
P5
5
GND
GND
Pad
Applications
Ethernet switch/router
PCI Express 3.0/2.1/1.1
PCIe jitter attenuation
DSL jitter attenuation
Broadcast video/audio timing
Processor and FPGA clocking
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
P6
6
7
8
9
10
11
12
Description
The Si5335 is a highly flexible clock generator capable of synthesizing four
completely non-integer-related frequencies up to 350 MHz. The device has four
banks of outputs with each bank supporting one differential pair or two single-ended
outputs. Using Silicon Laboratories' patented MultiSynth fractional divider
technology, all outputs are guaranteed to have 0 ppm frequency synthesis error
regardless of configuration, enabling the replacement of multiple clock ICs and
crystal oscillators with a single device. The Si5335 supports up to three independent,
pin-selectable device configurations, enabling one device to replace three separate
clock generators or buffer ICs. To ease system design, up to five user-assignable
and pin-selectable control pins are provided, supporting PCIe-compliant spread
spectrum control, master and/or individual output enables, frequency plan selection,
and device reset. Two selectable PLL loop bandwidths support jitter attenuation in
applications, such as PCIe and DSL. Through its flexible ClockBuilder™
(www.silabs.com/ClockBuilder) web configuration utility, factory-customized, pin-
controlled devices are available in two weeks without minimum order quantity
restrictions.
Rev. 1.2 1/13
Copyright © 2013 by Silicon Laboratories
VDDO3
VDD
CLK3B
CLK3A
LOS
P1
P2
Si5335
Si5335
Functional Block Diagram
Osc
PLL Bypass
÷MultiSynth0
PLL
PLL Bypass
÷MultiSynth1
OEB0
VDDO0
CLK0A
CLK0B
XA / CLKIN
XB / CLKINB
CLKIN
VDDO1
CLK1A
CLK1B
P1
P2
P3
P5
P6
Programmable
Pin Function
Options:
OEB0/1/2/3
OEB_all
SSENB
FS[1:0]
RESET
Control
PLL Bypass
÷MultiSynth2
PLL Bypass
÷MultiSynth3
OEB1
VDDO2
CLK2A
CLK2B
OEB2
VDDO3
CLK3A
CLK3B
OEB3
LOS
2
Rev. 1.2
Si5335
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical PCIe System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.10. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
5. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8. Loop Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9. Applications of the Si5335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
9.1. Free-Running Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2. Synchronous Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.3. Configurable Universal Buffer and Level Translator . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
14.1. Si5335 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Rev. 1.2
3
Si5335
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Symbol
T
A
Test Condition
Min
–40
2.97
Typ
25
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Unit
°C
V
V
V
V
Core Supply Voltage
V
DD
2.25
1.71
Output Buffer Supply
Voltage
V
DDOn
1.4
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
(Clock Generator Mode)
Core Supply Current
(Buffer Mode)
Symbol
I
DDCG
I
DDB
Test Condition
100 MHz on all outputs,
25 MHz refclk,
clock generator mode
50 MHz refclk
LVPECL, 350 MHz
CML, 350 MHz
LVDS, 350 MHz
HCSL, 250 MHz
2 pF load
SSTL, 350 MHz
CMOS, 50 MHz
15 pF load
1
CMOS, 200 MHz
1,2
3.3 V VDD0
CMOS, 200 MHz
1,2
2.5 V
CMOS, 200 MHz
1,2
1.8 V
HSTL, 350 MHz
Min
—
Typ
45
Max
60
Unit
mA
—
—
—
—
—
—
—
—
—
—
—
12
—
12
—
—
—
6
13
10
7
—
—
30
—
8
20
19
9
18
14
10
19
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Output Buffer Supply Current
I
DDOx
Notes:
1.
Single CMOS driver active.
2.
Measured into a 5” 50
trace with 2 pF load.
4
Rev. 1.2
Si5335
Table 3. Performance Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
PLL Acquisition Time
PLL Tracking Range
Symbol
t
ACQ
f
TRACK
f
BW1
f
BW2
Test Condition
1.6 MHz loop bandwidth
475 kHz or 1.6 MHz loop
bandwidth
High bandwidth option
Low bandwidth option
Output frequency < Fvco/8
Min
—
5000
—
—
0
—
0.01
—
Typ
—
20000
1.6
475
0
2.6
0.2
—
2.5
—
—
–0.45
31.5
Max
25
—
—
—
1
5
1
2
4
200
100
–0.5
33
Unit
ms
ppm
MHz
kHz
ppb
µs
µs
ms
ns
ns
ps
%
kHz
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
CLKIN Loss of Signal Detect
Time
CLKIN Loss of Signal Release
Time
POR to Output Clock Valid
Input-to-Output Propagation
Delay
Reset Minimum Pulse Width
Output-Output Skew
1
Spread Spectrum PP
Frequency Deviation
2
Spread Spectrum Modulation
Rate
3
f
RES
t
LOS
t
LOSRLS
t
RDY
t
PROP
t
RESET
t
DSKEW
SS
DEV
SS
DEV
Buffer Mode
(PLL Bypass)
—
—
F
OUT
> 5 MHz
F
OUT
= 100 MHz
F
OUT
= 100 MHz
—
—
30
Notes:
1.
Outputs at integer-related frequencies and using the same driver format.
2.
Default value is 0.5% down spread.
3.
Default value is 31.5 kHz for PCI compliance.
Rev. 1.2
5
实时操作系统RTOS
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