Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
11
DESCRIPTION
THE Hynix HY57V161610F-Series is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory
and graphic applications which require large memory density and high bandwidth. HY57V161610F-Series is organized
as 2banks of 524,288x16.
HY57V161610F-Series is offering fully synchronous operation referenced to a positive edge clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a '2N' rule.)
FEATURES
•
•
•
•
•
•
Voltage: VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of
pin pitch (Lead or Lead Free Package)
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
Internal two banks operation
•
•
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 1, 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
(V
DD
(min) of HY57V161610FT(P)-5(I) series is 3.15V)
Part No.
HY57V161610FT(P)-5(I)
HY57V161610FT(P)-6(I)
HY57V161610FT(P)-7(I)
HY57V161610FT(P)-H(I)
Clock Frequency
200MHz
166MHz
143MHz
133MHz
2Banks x 512Kbits x16I/O
LVTTL
400mil
50TSOPII
Organization
Interface
Package
Note: 1. HY57V161610FTP Series: Lead free, commercial temperature(0
o
C
~ 70
o
C.)
2. HY57V161610FT Series: Leaded, commercial temperature(0
o
C
~ 70
o
C.)
3.HY57V161610FTP-xxI Series: Lead free, Industrial temperature(-40
o
C
~ 85
o
C)
4.HY57V161610FT-xxI Series: Leaded, Industrial temperature(-40
o
C
~ 85
o
C)
Rev. 1.0 / Apr. 2006
2
Synchronous DRAM Memory 16Mbit (1Mx16bit)
HY57V161610FT(P)-xx(I) Series
11
PIN DESCRIPTION
SYMBOL
CLK
CKE
CS
BA
A0 ~ A10
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
SUPPLY
SUPPLY
-
DESCRIPTION
Clock: The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Clock Enable: Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among (deep) power down, suspend or self refresh
Chip Select: Enables or disables all inputs except CLK, CKE, and DQM
Bank Address: Select either one of banks during both RAS and CAS activity
Row Address: RA0 ~ RA10, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
Command Inputs: RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask: Controls output buffers in read mode and masks input data in write
mode
Data Input / Output: Multiplexed data input / output pin
Power supply for internal circuits
Power supply for output buffers
No connection : These pads should be left unconnected
Rev. 1.0 / Apr. 2006
4
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