Preliminary
GS8161ZV18A(T/D)/GS8161ZV32A(D)/GS8161ZV36A(T/D)
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
350 MHz–150 MHz
1.8 V V
DD
1.8 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait read-
write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
synchronous control of the output drivers and turn the RAM's output
drivers off at any time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by asynchronous
SRAMs and simplifies input signal timing.
The GS8161ZV18A(T/D)/GS8161ZV32A(D)/GS8161ZV36A(T/D)
may be configured by the user to operate in Pipeline or Flow Through
mode. Operating as a pipelined synchronous device, in addition to the
rising-edge-triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read cycles,
pipelined SRAM output data is temporarily stored by the edge
triggered output register during the access cycle and then released to
the output drivers at the next rising edge of clock.
The GS8161ZV18A(T/D)/GS8161ZV32A(D)/GS8161ZV36A(T/D)
is implemented with GSI's high performance CMOS technology and
is available in JEDEC-standard 100-pin TQFP and 165-bump FP-
BGA packages.
Functional Description
The GS8161ZV18A(T/D)/GS8161ZV32A(D)/GS8161ZV36A(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like
ZBT, NtRAM, NoBL or other pipelined read/double late write or flow
through read/single late write SRAMs, allow utilization of all
available bus bandwidth by eliminating the need to insert deselect
cycles when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and read/
write control inputs are captured on the rising edge of the input clock.
Burst order control (LBO) must be tied to a power rail for proper
operation. Asynchronous inputs include the Sleep mode enable, ZZ
and Output Enable. Output Enable can be used to override the
Parameter Synopsis
-350
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
1.8
2.85
395
455
4.5
4.5
270
305
-333
2.0
3.0
370
430
4.7
4.7
250
285
-300
2.2
3.3
335
390
5.0
5.0
230
270
-250
2.3
4.0
280
330
5.5
5.5
210
240
-200
2.7
5.0
230
270
6.5
6.5
185
205
-150
3.3
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow
Through
2-1-1-1
Rev: 1.00a 6/2003
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1/35
© 2003, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8161ZV18A(T/D)/GS8161ZV32A(D)/GS8161ZV36A(T/D)
100-Pin TQFP Pin Descriptions
Symbol
A
0
, A
1
A
2–
A
18
A
19
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
—
I/O
I/O
I/O
I/O
In
In
In
In
In
In
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Address Input
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Core power supply
Ground
Output driver power supply
Rev: 1.00a 6/2003
4/35
© 2003, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
